Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
11/2011
11/22/2011US8064275 Local sensing and feedback for an SRAM array
11/22/2011US8064273 Memory device and methods thereof
11/22/2011US8064271 Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same
11/22/2011US8064270 Semiconductor integrated circuit device
11/22/2011US8064269 Apparatus and methods having majority bit detection
11/22/2011US8064268 Method and system for a serial peripheral interface
11/22/2011US8064265 Programming bit alterable memories
11/22/2011US8064257 Semiconductor memory device having faulty cells
11/22/2011US8064237 Identifying and accessing individual memory devices in a memory channel
11/22/2011US8064222 Semiconductor integrated circuit device
11/22/2011US8061895 Semiconductor device
11/22/2011CA2502655C Recording medium, method of configuring control information thereof, recording and/or reproducing method using the same, and apparatus thereof
11/17/2011WO2011094437A3 Memory access methods and apparatus
11/17/2011WO2011091073A3 Duty cycle correction circuit for memory interfaces in integrated circuits
11/17/2011US20110280094 Boost Cell Supply Write Assist
11/17/2011US20110280093 Data protective structure, electronic device, and method of erasing data
11/17/2011US20110280092 Multi-Bank Read/Write To Reduce Test-Time In Memories
11/17/2011US20110280090 Semiconductor device and test method thereof
11/17/2011US20110280089 Data bus power-reduced semiconductor storage apparatus
11/17/2011US20110280088 Single supply sub vdd bitline precharge sram and method for level shifting
11/17/2011US20110280086 Semiconductor memory device and semiconductor memory system
11/17/2011US20110280061 Semiconductor device
11/17/2011US20110280060 Write buffering systems for accessing multiple layers of memory in integrated circuits
11/17/2011US20110280058 Nonvolatile memory device
11/17/2011US20110280057 Memory Device Having A Local Current Sink
11/17/2011DE102011075814A1 Speicherpuffer mit zugänglicher Information nach einem Schreibfehler Memory buffer with accessible information after a write error
11/16/2011EP2387039A1 Hierarchical buffered segmented bit-lines based sram
11/16/2011CN202042197U Three-dimensional media player
11/16/2011CN202042196U Multifunctional player
11/16/2011CN202042195U Novel universal serial bus (USB) flash disk
11/16/2011CN202042194U U disk convenient to carry
11/16/2011CN202042193U U disk storage module and U disk
11/16/2011CN202042192U Easily-assembled U disk component and U disk
11/16/2011CN1794580B Delay locked loop for use in semiconductor memory device and method thereof
11/16/2011CN1685438B Device and method for biasing threshold voltage in DRAM sensing
11/16/2011CN102246236A Self-tuning of signal path delay in circuit employing multiple voltage domains
11/16/2011CN102243890A Read-write protection circuit
11/16/2011CN102243889A Mobile terminal and method for executing application program according to user input
11/16/2011CN102243888A Storage cell with balance load of multi-port register
11/16/2011CN101782878B Data storing method based on distributed memory
11/16/2011CN101425323B Dual-port data storage device
11/16/2011CN101356584B Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
11/16/2011CN101273413B Portable data memory using single layer unit and multi-layer unit flash memory
11/15/2011US8060928 Information-processing apparatus, method for controlling information-processing apparatus, and storage medium
11/15/2011US8060669 Memory controller with automatic command processing unit and memory system including the same
11/15/2011US8060553 Service oriented architecture for a transformation function in a data integration platform
11/15/2011US8059921 Associating audio and image data
11/15/2011US8059481 Semiconductor memory device
11/15/2011US8059480 Semiconductor memory device
11/15/2011US8059476 Control component for controlling a delay interval within a memory component
11/15/2011US8059474 Reducing read failure in a memory device
11/15/2011US8059454 Adjustable write pulse generator within a chalcogenide memory device
11/15/2011US8059448 Semiconductor memory device with variable resistance elements
11/15/2011CA2712949C A radio frequency circuit board topology
11/15/2011CA2443839C System, method, and article of manufacture for using a replaceable component to select a replaceable quality of service capable network communication channel component
11/10/2011WO2011140033A2 Techniques for refreshing a semiconductor memory device
11/10/2011WO2011137541A1 Method and apparatus for concurrently reading a plurality of memory devices using a single buffer
11/10/2011WO2011116316A3 Method and apparatus for suppressing bitline coupling through miller capacitance to a sense amplifier interstitial node
11/10/2011WO2011100221A3 Memory device including a memory block having a fixed latency data output
11/10/2011US20110276731 Dual-port functionality for a single-port cell memory device
11/10/2011US20110273951 Memory circuit and method for controlling memory circuit
11/10/2011US20110273945 Techniques to improve the operations of a memory device
11/10/2011US20110273944 Semiconductor memory device and method of operating the same
11/10/2011US20110273943 System and Method to Read a Memory Cell with a Complementary Metal-Oxide-Semiconductor (CMOS) Read Transistor
11/10/2011US20110273942 Memory Array Having a Programmable Word Length, and Method of Operating Same
11/10/2011US20110273941 Techniques for refreshing a semiconductor memory device
11/10/2011US20110273940 Level shifting circuit
11/10/2011US20110273938 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
11/10/2011US20110273928 Method and system for providing a magnetic magnetic field aligned spin transfer torque random access memory
11/10/2011US20110273923 Pass-gated bump sense amplifier for embedded drams
11/10/2011US20110273922 Sense amplifier using reference signal through standard mos and dram capacitor
11/10/2011CA2798868A1 Method and apparatus for concurrently reading a plurality of memory devices using a single buffer
11/09/2011CN202034057U Vehicular audio playing system
11/09/2011CN202034056U Multifunctional MP3 (MPEG Audio 3)
11/09/2011CN202034055U MP3 (MPEG Audio 3), MP4 (MPEG Audio 4) and recorder pen with super bass function
11/09/2011CN202034054U Audio playing system and earphones
11/09/2011CN202034053U USB (universal serial bus) disk with LED (light-emitting diode) illuminating system
11/09/2011CN202034052U Name card type flash disk
11/09/2011CN202033603U Multipurpose watch type USB flash disc
11/09/2011CN1905062B Ferroelectric memory device
11/09/2011CN1811986B Semiconductor device, semiconductor memory device and method for applying memory cell power voltage
11/09/2011CN1747063B Semiconductor memory devices
11/09/2011CN102239524A Logical unit operation
11/09/2011CN102239523A Switched interface stacked-die memory architecture
11/09/2011CN102237127A Computer shutdown state music playing circuit configuration
11/09/2011CN102237126A Tone generation apparatus
11/09/2011CN102236627A Interface device
11/09/2011CN101527164B Data reading circuit and method
11/09/2011CN101276637B Register read mechanism
11/09/2011CN101271729B Content data storage device and its control method
11/09/2011CN101067965B Write-side calibration for data interface
11/08/2011US8054708 Power-on detector, operating method of power-on detector and memory device including the same
11/08/2011US8054707 Low energy memory component
11/08/2011US8054706 Sensor protection using a non-volatile memory cell
11/08/2011US8054705 Semiconductor integrated circuit
11/08/2011US8054703 Active termination circuit and method for controlling the impedance of external integrated circuit terminals
11/08/2011US8054702 Semiconductor memory device with signal aligning circuit
11/08/2011US8054701 Delay locked loop and semiconductor memory device with the same
11/08/2011US8054700 Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device
11/08/2011US8054699 Semiconductor memory device having a double branching bidirectional buffer
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