Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
04/2009
04/07/2009US7515495 Active cycle control circuit and method for semiconductor memory apparatus
04/07/2009US7515494 Refresh period adjustment technique for dynamic random access memories (DRAM) and integrated circuit devices incorporating embedded DRAM
04/07/2009US7515493 Sensing circuit for semiconductor memories
04/07/2009US7515492 Semiconductor memory device
04/07/2009US7515491 Method for evaluating leakage effects on static memory cell access time
04/07/2009US7515490 Sensing circuit for organic memory
04/07/2009US7515486 Multimode data buffer and method for controlling propagation delay time
04/07/2009US7515484 Page buffer circuit of memory device and program method
04/07/2009US7515483 Page buffer flash memory device and programming method using the same
04/07/2009US7515482 Pipe latch device of semiconductor memory device
04/07/2009US7515461 Current compliant sensing architecture for multilevel phase change memory
04/07/2009US7515459 Method of programming a memory cell array using successive pulses of increased duration
04/07/2009US7515159 Reconfigurable address generation circuit for image processing, and reconfigurable LSI comprising the same
04/07/2009US7514964 Universal programmable logic gate and routing method
04/07/2009US7514954 Method and apparatus for output driver calibration
04/07/2009CA2507261C An in-home digital video unit with combined archival storage and high-access storage
04/04/2009CA2629752A1 Method and system for updating a stored data value in a non-volatile memory
04/02/2009WO2009042528A1 System and method for processing signals in high speed dram
04/02/2009WO2007137062A3 Methods and apparatus to provide voltage control for sram write assist circuits
04/02/2009US20090086560 Memory device with self refresh cycle control function
04/02/2009US20090086559 Semiconductor memory device and driving method thereof
04/02/2009US20090086557 Synchronous semiconductor memory device and method for driving the same
04/02/2009US20090086556 Methods and apparatuses for operating memory
04/02/2009US20090086555 Voltage supply circuit and semiconductor memory
04/02/2009US20090086554 System and Method for Operating a Semiconductor Memory
04/02/2009US20090086553 Semiconductor memory device and method of inputting and outputting data in the semiconductor memory device
04/02/2009US20090086552 Semiconductor memory device and its driving method
04/02/2009US20090086551 Semiconductor device
04/02/2009US20090086550 Semiconductor memory device
04/02/2009US20090086545 Non-Volatile Memory Device and Method of Operating the Same
04/02/2009US20090086543 Highly Compact Non-Volatile Memory And Method Thereof
04/02/2009US20090086538 Method and apparatus for programming memory cell array
04/02/2009US20090086536 Semiconductor device
04/02/2009US20090086534 Apparatus and method for implementing precise sensing of pcram devices
04/02/2009US20090086532 Magnetic random access memory
04/02/2009US20090086529 Semiconductor storage device
04/02/2009DE19919904B4 Anordnung von Dateneingabe-/-Ausgabeschaltungen zur Verwendung in einem Halbleiterspeicherbauelement Arrangement of data entry - / - output circuits for use in a semiconductor memory device
04/02/2009DE102008036822A1 Verfahren zum Speichern von Daten in einem Solid-State-Speicher, Solid-State-Speichersystem und Computersystem A method of storing data in a solid-state memory, solid state storage system and computer system
04/02/2009DE102006043668B4 Steuerbaustein zur Steuerung eines Halbleiterspeicherbausteins eines Halbleiterspeichermoduls Control module for controlling a semiconductor memory device of a semiconductor memory module
04/02/2009DE102006022867B4 Ausleseschaltung für oder in einem ROM-Speicher und ROM-Speicher Readout circuitry for or in a ROM memory and ROM memory
04/02/2009DE102004039236B4 Magnetischer Speicher Magnetic memory
04/01/2009EP2043103A2 Electronic memory device
04/01/2009EP2041752A2 Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
04/01/2009EP2041751A2 Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory
04/01/2009EP2041750A2 Memories with front end precharge
04/01/2009CN201215724Y Cloth type vehicle-mounted wireless transmission multifunctional MP3
04/01/2009CN201213506Y Waistband head with MP3 function
04/01/2009CN201213503Y Waistband head with various article functions
04/01/2009CN101401167A Memory device distributed controller system
04/01/2009CN101401165A Double data rate interface
04/01/2009CN101401106A Method of reducing electro-static discharge (esd) from conductors on insulators
04/01/2009CN101399084A Memory devices
04/01/2009CN101399078A Synchronous semiconductor memory device and method for driving the same
04/01/2009CN101399077A High-speed, low-power input buffer for integrated circuit devices
04/01/2009CN101399076A Electronic data flash memory card, method for control and method for determining type of flash memory
04/01/2009CN101399075A Electronic data flash memory card with flash memory bad block management
04/01/2009CN101399074A Memory circuit in integrated circuit and controlling method thereof
04/01/2009CN101399073A 半导体存储器装置 The semiconductor memory device
04/01/2009CN101398605A Mutual integration expansion base and mini projector
04/01/2009CN100474779C Encoding up/down based D-A converter and delayed phase locking loop device and method therefor
04/01/2009CN100474457C Test method for a semiconductor memory
04/01/2009CN100474449C Block switch in flash memory device
04/01/2009CN100474447C Semiconductor memory device
04/01/2009CN100474446C Semiconductor memory device
04/01/2009CN100474445C Semiconductor memory device using vss or vdd bit line precharge approach
04/01/2009CN100474442C Fault removing circuit for storage and power control method thereof
04/01/2009CN100474439C Electric resistance cross-point memory, recalibration testing method, and self-calibration electric resistance cross-point memory array chip
04/01/2009CN100474437C Magnetic RAM
04/01/2009CN100474436C Methods and apparatus for delay circuit
04/01/2009CN100474435C Read amplifier and electronic apparatus using the same
04/01/2009CN100474434C Integrated circuit memory devices and operating methods configured to output data bits at a lower rate
03/2009
03/31/2009US7512971 Method and system for enabling remote access to a computer system
03/31/2009US7512908 Method and apparatus for improving SRAM cell stability by using boosted word lines
03/31/2009US7512845 Semiconductor memory device and method for stacking reference data
03/31/2009US7512763 Transparent SDRAM in an embedded environment
03/31/2009US7512027 Refresh control circuit in semiconductor memory apparatus and method of controlling period of refresh signal using the same
03/31/2009US7512026 Sense amplifying circuit capable of operating with lower voltage and nonvolatile memory device including the same
03/31/2009US7512025 Open digit line array architecture for a memory array
03/31/2009US7512023 Memory and method for improving the reliability of a memory having a used memory region and an unused memory region
03/31/2009US7512021 Register configuration control device, register configuration control method, and program for implementing the method
03/31/2009US7512020 Nonvolatile memory device with load-free wired-OR structure and an associated driving method
03/31/2009US7512019 High speed digital signal input buffer and method using pulsed positive feedback
03/31/2009US7512018 Column address enable signal generation circuit for semiconductor memory device
03/31/2009US7512009 Method for programming a reference cell
03/31/2009US7511988 Static noise-immune SRAM cells
03/31/2009US7511569 Circuit for supplying a voltage in a memory device
03/31/2009US7511562 High voltage generating circuit preserving charge pumping efficiency
03/31/2009US7510957 Complimentary lateral III-nitride transistors
03/26/2009WO2009039169A1 Refreshing data of memory cells with electrically floating body transistors
03/26/2009WO2009038914A2 Twisted input pair of first gain stage for high signal integrity in cmos image sensor
03/26/2009WO2009037697A2 Improved systems and methods for determining logical values of coupled flash memory cells
03/26/2009WO2008153652A4 Reference clock and command word alignment
03/26/2009WO2008127698A3 Memory system with point-to-point request interconnect
03/26/2009US20090080278 Circuit and method for reducing power in a memory device during standby modes
03/26/2009US20090080277 Memory cell fuse circuit and controlling method thereof
03/26/2009US20090080276 Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits
03/26/2009US20090080275 Reducing bit line leakage current in non-volatile memories
03/26/2009US20090080274 Memory control circuit and semiconductor device
03/26/2009US20090080272 Delay locked loop circuit for a synchronous semiconductor memory device and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device
03/26/2009US20090080271 Memory Cell, Memory Device, Device and Method of Accessing a Memory Cell