Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
04/2010
04/01/2010US20100080040 Nonvolatile memory device and method of driving the same
04/01/2010US20100080039 Nonvoltile memory device and method of driving the same
04/01/2010US20100080038 Semiconductor memory device
04/01/2010US20100080033 Volatile memory elements with soft error upset immunity
04/01/2010DE19648752B4 Befehlsausführungsverfahren für ein CD-ROM Laufwerk Instruction execution method for a CD-ROM drive
04/01/2010DE102004011732B4 Integrierter Speicherbaustein mit Verzögerungsregelkreis Integrated memory device with delay locked loop
04/01/2010DE10084797B4 Schaltung und Verfahren zum Erfassen von mehreren Gleichheiten in Assoziativspeichern Circuit and method for detecting a plurality of associative memories in equalities
03/2010
03/31/2010EP2168128A1 Memory device with delay tracking for improved timing margin
03/31/2010CN201435221Y Music player
03/31/2010CN201435215Y Portable device applying network for storage
03/31/2010CN201432624Y Vehicle MP3 device
03/31/2010CN101689401A Nano-vacuum-tubes and their application in storage devices
03/31/2010CN101689395A Systems and methods for determining refresh rate of memory based on RF activities
03/31/2010CN101686615A Portable electronic device
03/31/2010CN101685665A Mobile storage device and connector thereof
03/31/2010CN101685664A Monolithic integration USB HOST MP3/WMA decoding chip
03/31/2010CN101685663A Portable memory device for controlling joint by moving elements
03/31/2010CN101685662A Multimedia player of double extension cassette
03/31/2010CN101684963A Air conditioner with voice broadcast function
03/31/2010CN101683797A Adjustable clamping sleeve reading device internally installed with coordinate circuit system, conductive socket and conductive
03/30/2010US7690029 Remote administration of smart cards for secure access systems
03/30/2010US7689879 System and method for on-board timing margin testing of memory modules
03/30/2010US7689741 Dual buffer memory system for reducing data transmission time and control method thereof
03/30/2010US7688670 Semiconductor device with improved power supply control for a plurality of memory arrays
03/30/2010US7688669 Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages
03/30/2010US7688668 Controlling power supply to memory cells
03/30/2010US7688662 Method for hiding a refresh in a pseudo-static memory
03/30/2010US7688661 Semiconductor memory device, and method of controlling the same
03/30/2010US7688660 Semiconductor device, an electronic device and a method for operating the same
03/30/2010US7688658 Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof
03/30/2010US7688657 Apparatus and method for generating test signals after a test mode is completed
03/30/2010US7688653 Method and system for improved efficiency of synchronous mirror delays and delay locked loops
03/30/2010US7688652 Storage of data in memory via packet strobing
03/30/2010US7688651 Methods and devices for regulating the timing of control signals in integrated circuit memory devices
03/30/2010US7688650 Write control method for a memory array configured with multiple memory subarrays
03/30/2010US7688649 Semiconductor memory device with debounced write control signal
03/30/2010US7688648 High speed flash memory
03/30/2010US7688646 Non-volatile latch circuit for restoring data after power interruption
03/30/2010US7688645 Output circuit for a semiconductor memory device and data output method
03/30/2010US7688644 Semiconductor memory device and its driving method
03/30/2010US7688634 Method of operating an integrated circuit having at least one memory cell
03/30/2010US7688613 Method and system for controlling multiple electrical fuses with one program device
03/30/2010US7688129 System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
03/30/2010US7687347 Embedded flash memory devices on SOI substrates and methods of manufacture thereof
03/25/2010WO2010033317A1 Memory having self-timed bit line boost circuit and method therefor
03/25/2010WO2010031160A1 Mass data storage system with non-volatile memory modules
03/25/2010WO2009155474A3 Memory cell employing reduced voltage
03/25/2010WO2009154906A3 Apparatus and method for multi-phase clock generation
03/25/2010US20100074042 Semiconductor memory device
03/25/2010US20100074041 Semiconductor device including asymmetric sense amplifier
03/25/2010US20100074040 Method and Apparatus for Measuring Statistics of Dram Parameters with Minimum Perturbation to Cell Layout and Environment
03/25/2010US20100074039 Semiconductor memory device and method for testing the same
03/25/2010US20100074038 Memory Dies for Flexible Use and Method for Configuring Memory Dies
03/25/2010US20100074037 Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay
03/25/2010US20100074036 Current mode memory apparatus, systems, and methods
03/25/2010US20100074035 Semiconductor memory device
03/25/2010US20100074034 Voltage regulator with reduced sensitivity of output voltage to change in load current
03/25/2010US20100074032 Memory having self-timed bit line boost circuit and method therefor
03/25/2010US20100074031 Test mode signal generator for semiconductor memory and method of generating test mode signals
03/25/2010US20100074030 Adaptive regulator for idle state in a charge pump circuit of a memory device
03/25/2010US20100074024 Programming a memory device to increase data reliability
03/25/2010US20100074020 Charge pump operation in a non-volatile memory device
03/25/2010US20100074018 Read operation for non-volatile storage with compensation for coupling
03/25/2010US20100074014 Data state-based temperature compensation during sensing in non-volatile memory
03/25/2010US20100074011 Non-volatile memory device and page buffer circuit thereof
03/25/2010US20100074010 Memory device reference cell programming method and apparatus
03/25/2010US20100074000 Analog Access Circuit for Validating Chalcogenide Memory Cells
03/25/2010US20100073999 Semiconductor integrated circuit
03/25/2010US20100073998 Data writing method for magnetoresistive effect element and magnetic memory
03/25/2010US20100073997 Piezo-driven non-volatile memory cell with hysteretic resistance
03/25/2010US20100073993 Multi-resistive integrated circuit memory
03/25/2010US20100073992 Semiconductor memory device
03/25/2010US20100073991 Storage apparatus
03/25/2010US20100073990 Contemporaneous margin verification and memory access fr memory cells in cross point memory arrays
03/25/2010US20100073983 Nonvolatile semiconductor memory device and writing method of the same
03/25/2010US20100073982 Semiconductor device and method for designing the same
03/25/2010DE102004040962B4 Schaltung und Verfahren zur Kompensation eines Signalversatzes und zugehöriger Speicherbaustein Circuit and method for compensating for a signal offset and the associated memory module
03/25/2010DE10065477B4 Automatisches Vorladegerät einer Halbleiter-Speicheranordnung Auto precharge a semiconductor memory device
03/25/2010CA2774396A1 Mass data storage system with non-volatile memory modules
03/24/2010EP2166540A1 Semiconductor memory
03/24/2010EP2165412A1 Apparatus for sensorless positioning with signal amplifier
03/24/2010CN201430615Y Telephone set with flash disk function
03/24/2010CN201429990Y Safety USB disk
03/24/2010CN201429987Y Usb
03/24/2010CN201426572Y Acousto-optic photo frame
03/24/2010CN101681678A Delta sigma sense amplifier comprising digital filters and memory
03/24/2010CN101681677A Partial block erase architecture for flash memory
03/24/2010CN101681674A Memory device with delay tracking for improved timing margin
03/24/2010CN101681673A Tree type bit line decoder architecture for nor-type memory array
03/24/2010CN101681672A Memory architecture having local column select lines
03/24/2010CN101681671A Method and apparatus for reducing leakage current in memory arrays
03/24/2010CN101681670A Clock synchronization in a memory system
03/24/2010CN101681669A Semi-shared sense amplifier and global read line architecture
03/24/2010CN101681668A Division-based sensing and partitioning of electronic memory
03/24/2010CN101681667A Sense amplifier with stages to reduce capacitance mismatch in current mirror load
03/24/2010CN101681666A Sensing device for floating body cell memory and method thereof
03/24/2010CN101677108A 非易失性存储装置 Non-volatile memory device
03/24/2010CN101677019A Production line reading method and system of flash memory
03/24/2010CN101677013A Dual-system U disk
03/24/2010CN101676872A Structure of solid state disk and method for accelerating initialization thereof
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