Patents
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
01/1999
01/13/1999EP0812437A4 Performing speculative system memory reads
01/13/1999CN1204892A Memory address generator in convolutional interleaver/deinterleaver
01/13/1999CN1204820A Display memory control apparatus
01/13/1999CN1204819A Apparatus and method for data processing
01/13/1999CN1204808A PC card, connector and PC card connection structure
01/13/1999CN1204807A Memory device with small computer system interface
01/13/1999CN1204806A Data management apparatus, data management method, and recording medium
01/13/1999CN1204805A Method and device for saving memory
01/12/1999US5860159 Multiprocessing system including an apparatus for optimizing spin--lock operations
01/12/1999US5860158 Cache control unit with a cache request transaction-oriented protocol
01/12/1999US5860157 Nonvolatile memory card controller with an optimized memory address mapping window scheme
01/12/1999US5860153 Memory efficient directory coherency maintenance
01/12/1999US5860151 Data cache fast address calculation system and method
01/12/1999US5860150 Instruction pre-fetching of a cache line within a processor
01/12/1999US5860149 Memory buffer system using a single pointer to reference multiple associated data
01/12/1999US5860147 For translating a virtual address into a physical address
01/12/1999US5860146 Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces
01/12/1999US5860145 Address translation device storage last address translation in register separate from TLB
01/12/1999US5860144 Addressing method and system for providing access of a very large size physical memory buffer to a number of processes
01/12/1999US5860143 Real-time image data access from virtual memory in a digital printing system
01/12/1999US5860142 Method and apparatus for mapping the memory system of a computer for maximizing memory usage
01/12/1999US5860141 Method and apparatus for enabling physical memory larger than corresponding virtual memory
01/12/1999US5860139 BIOS memory address decoder for providing an extended BIOS memory address space by reclaiming a portion of non-BIOS address space
01/12/1999US5860138 Processor with compiler-allocated, variable length intermediate storage
01/12/1999US5860136 Method and apparatus for use of associated memory with large key spaces
01/12/1999US5860135 File managing device of a non-volatile memory, a memory card and method for controlling a file system
01/12/1999US5860133 Method for altering memory configuration and sizing memory modules while maintaining software code stream coherence
01/12/1999US5860132 Storage dispersal system based on related, shared data storage space reservation
01/12/1999US5860131 Method for providing dynamic cache management in a computer system
01/12/1999US5860130 Memory interface apparatus including an address modification unit having an offset table for prestoring a plurality of offsets
01/12/1999US5860127 Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
01/12/1999US5860124 Method for performing a continuous over-write of a file in nonvolatile memory
01/12/1999US5860123 One-chip CPU
01/12/1999US5860121 Method and apparatus for programming electrically reprogrammable non-volatile memory and a unit including such apparatus
01/12/1999US5860120 Within a computer system
01/12/1999US5860118 SRAM write partitioning
01/12/1999US5860117 Central processing unit of a computer
01/12/1999US5860116 Computer system
01/12/1999US5860114 Method and apparatus for managing snoop requests using snoop advisory cells
01/12/1999US5860113 System for using a dirty bit with a cache memory
01/12/1999US5860112 Method and apparatus for blending bus writes and cache write-backs to memory
01/12/1999US5860111 In a multi-master computer system
01/12/1999US5860110 Conference maintenance method for cache memories in multi-processor system triggered by a predetermined synchronization point and a predetermined condition
01/12/1999US5860109 Methods and apparatus for a coherence transformer for connecting computer system coherence domains
01/12/1999US5860108 Method and clustered multi-processor system for controlling a clock phase for clusters
01/12/1999US5860107 Processor and method for store gathering through merged store operations
01/12/1999US5860106 Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem
01/12/1999US5860105 NDIRTY cache line lookahead
01/12/1999US5860102 Cache memory circuit
01/12/1999US5860101 Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory
01/12/1999US5860100 Data processing system
01/12/1999US5860099 Stored program system with protected memory and secure signature extraction
01/12/1999US5860098 Process for running a computer program subject to interrupt
01/12/1999US5860097 For a computer
01/12/1999US5860096 Multi-level instruction cache for a computer
01/12/1999US5860095 Conflict cache having cache miscounters for a computer memory system
01/12/1999US5860094 System for protecting information stored on physical media
01/12/1999US5860093 In a data system
01/12/1999US5860092 Apparatus and method for addressing a cache memory in a computer system utilizing cache tag memory with integrated adder and pre-decode circuit
01/12/1999US5860091 Method and apparatus for efficient management of non-aligned I/O write request in high bandwidth raid applications
01/12/1999US5860087 Data search method wherein the court-key-data (CKD) storage subsystem disconnects from the central processing unit when searching
01/12/1999US5860083 Data storage system having flash memory and disk drive
01/12/1999US5860082 Method and apparatus for allocating storage in a flash memory
01/12/1999US5860081 Interfacing an L2 cache to a single bus having alternative protocols
01/12/1999US5860080 Multicasting system for selecting a group of memory devices for operation
01/12/1999US5860079 Arrangement and method for efficient calculation of memory addresses in a block storage memory system
01/12/1999US5860078 Multiple input two-level cache directory with mini-directory for initial comparisons and main directory for mini-directory misses
01/12/1999US5860077 Three-dimensional data storing method for parallel access of vertex data
01/12/1999US5860076 48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses
01/12/1999US5860074 Method and apparatus for displaying an electronic document with text over object
01/12/1999US5860028 I/O bus expansion system wherein processor checks plurality of possible address until a response from the peripheral selected by address decoder using user input
01/12/1999US5860027 Data processing system
01/12/1999US5860025 Precharging an output peripheral for a direct memory access operation
01/12/1999US5859978 Managing application programs in a computer network by using a database of application objects
01/12/1999US5859971 Differencing client/server communication system for use with CGI forms
01/12/1999US5859966 Security system for computer systems
01/12/1999US5859961 Renumbered array architecture for multi-array memories
01/12/1999US5859960 Semiconductor disk apparatus having a semiconductor memory for a recording medium
01/12/1999US5859911 Method for the secure remote flashing of the BIOS of a computer
01/12/1999US5859858 Method and apparatus for correcting a multilevel cell memory by using error locating codes
01/12/1999US5859806 Semiconductor memory device and computer
01/12/1999US5859804 Method and apparatus for real time two dimensional redundancy allocation
01/12/1999US5859795 Multi-level memory circuits and corresponding reading and writing methods
01/12/1999US5859649 Data processing system having display controller with bursting direct memory access
01/12/1999US5859646 Graphic drawing processing device and graphic drawing processing system using thereof
01/12/1999CA2090198C Teamwork cad system and process for teamwork designing
01/10/1999CA2241909A1 Cache coherent network, network adapter and message protocol for scalable shared memory processing systems
01/07/1999WO1999000939A1 Shared memory management in a switched network element
01/07/1999WO1999000774A1 Security module comprising means generating links between main files and auxiliary files
01/07/1999WO1999000738A1 Method and apparatus for dynamic queue sizing
01/07/1999WO1999000735A1 Virtual address access to tiled surfaces
01/07/1999WO1999000733A1 Method and apparatus for managing hashed objects
01/07/1999WO1999000732A1 Bounded-pause time garbage collection system and method including write barrier associated with source and target instances of a partially relocated object
01/07/1999WO1999000730A1 Bounded-pause time garbage collection system and method including write barrier associated with a source instance of a partially relocated object
01/07/1999WO1999000729A1 Bounded-pause time garbage collection system and method including read and write barriers associated with an instance of a partially relocated object
01/07/1999WO1999000728A1 File managing device, file managing method, and recording medium stored with file managing program
01/07/1999WO1999000727A1 Storage of multiple host storage management information
01/07/1999WO1999000725A1 Method and apparatus for managing a linked-list data structure
01/07/1999WO1999000718A1 Self-unpredictable microprocessor or microcomputer
01/07/1999WO1998045987A3 Arrangement for improving availability of services in a communication system