| Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643) |
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| 01/09/2007 | US7161436 Charge pump structure for reducing capacitance in loop filter of a phase locked loop |
| 01/09/2007 | US7161435 Feedback control circuit |
| 01/09/2007 | US7161417 Loop filter and method for generating stable control voltage of the same |
| 01/09/2007 | US7161402 Programmable delay locked loop |
| 01/09/2007 | US7161401 Wide output-range charge pump with active biasing current |
| 01/09/2007 | US7161400 Phase synchronization for wide area integrated circuits |
| 01/09/2007 | US7161398 VCDL-based dual loop DLL having infinite phase shift function |
| 01/09/2007 | US7161397 Digital delay locked loop capable of correcting duty cycle and its method |
| 01/09/2007 | US7161396 CMOS power on reset circuit |
| 01/09/2007 | CA2442876C Timesliced discrete-time phase locked loop |
| 01/04/2007 | WO2007000712A1 Synchronization scheme with adaptive reference frequency correction |
| 01/04/2007 | WO2007000060A2 Software controlled clock synthesizer |
| 01/04/2007 | US20070004371 IC receiver to minimize tracking error |
| 01/04/2007 | US20070002990 Data recovery using data eye tracking |
| 01/04/2007 | US20070002965 Dual link DVI transmitter serviced by single phase locked loop |
| 01/04/2007 | US20070001770 Phase lock loop and operating method thereof |
| 01/04/2007 | US20070001724 Delay locked loop circuit |
| 01/04/2007 | US20070001723 Clock and data recovery circuit and method thereof |
| 01/04/2007 | US20070001722 Recovery of Client Clock Without Jitter |
| 01/04/2007 | US20070001721 Power-on reset circuit |
| 01/04/2007 | US20070001720 System and method for monitoring a power supply level |
| 01/04/2007 | US20070001661 Delay-locked loop and a method of testing a delay-locked loop |
| 01/04/2007 | DE10207315B4 Vorrichtung zur Datenrückgewinnung aus einem empfangenen Datensignal An apparatus for recovering data from a received data signal |
| 01/04/2007 | DE102005036559B3 Input clock signal synchronizing device, for dynamic RAM, has control devices regulating time delays of clock signals based on phase determined by respective phase comparison devices |
| 01/04/2007 | DE102005030356A1 Digitaler Phasenregelkreis und Verfahren zur Regelung eines digitalen Phasenregelkreises Digital phase-locked loop and method of controlling a digital phase-locked loop |
| 01/04/2007 | DE10130732B4 Signalübertragungsschaltung, Datenpufferschaltung und Signalübertragungsverfahren Signal transmission circuit, the data buffer circuit, and signal transmission method |
| 01/03/2007 | EP1738476A2 System for synchronizing a portable transceiver to a network |
| 01/03/2007 | EP1738465A1 Fast phase-frequency detector arrangement |
| 01/03/2007 | EP1297619B1 Linear dead-band-free digital phase detection |
| 01/03/2007 | EP1282847B1 Digital clock generator |
| 01/03/2007 | CN1890881A Delta-sigma type fraction division pll synthesizer |
| 01/03/2007 | CN1889684A Long-distance monitoring business realizing method, system and terminal equipment between video information terminals |
| 01/03/2007 | CN1889535A Method and system for processing multi-media value-added business information and utilized gate equipment |
| 01/03/2007 | CN1889520A Route information update method and network equipment based on OSPF |
| 01/03/2007 | CN1889365A Radio frequency double-channel voltage controlled oscillator based on central tapped inductive switch |
| 01/03/2007 | CN1889364A Clock generating device based on lock-phase ring |
| 01/02/2007 | US7159204 System and method for design entry and synthesis in programmable logic devices |
| 01/02/2007 | US7159134 Method and apparatus for clock and power control in wireless systems |
| 01/02/2007 | US7158767 Tuneable frequency translator |
| 01/02/2007 | US7158727 10 Gbit/sec transmit structure with programmable clock delays |
| 01/02/2007 | US7158603 Method and apparatus for compensating deviation variances in a 2-level FSK FM transmitter |
| 01/02/2007 | US7158602 Phase locked loop circuit and clock reproduction circuit |
| 01/02/2007 | US7158600 Charge pump phase locked loop |
| 01/02/2007 | US7158593 Combining a clock signal and a data signal |
| 01/02/2007 | US7158587 Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof |
| 01/02/2007 | US7158443 Delay-lock loop and method adapting itself to operate over a wide frequency range |
| 01/02/2007 | US7157985 PLL modulation circuit and polar modulation apparatus |
| 01/02/2007 | US7157980 Clock converter and electronic apparatus with the same |
| 01/02/2007 | US7157979 Phase-lock loops |
| 01/02/2007 | US7157978 Method and system for a lock detector for a phase-locked loop |
| 01/02/2007 | US7157954 Semiconductor type two phase locked loop filter |
| 01/02/2007 | US7157950 Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains |
| 01/02/2007 | US7157949 Delay locked loop capable of preventing false lock and method thereof |
| 01/02/2007 | US7157948 Method and apparatus for calibrating a delay line |
| 12/28/2006 | WO2006137324A1 Wireless receiver |
| 12/28/2006 | WO2006137238A1 Phase correcting circuit |
| 12/28/2006 | WO2006137031A2 Phase-locked loop systems using adaptive low-pass filters in switched bandwidth feedback loops |
| 12/28/2006 | WO2006137030A1 Phase-locked loop systems using static phase offset calibration |
| 12/28/2006 | WO2006136089A1 A method and system for implementing two-way interworking operation of circuit domain and packet domain |
| 12/28/2006 | WO2005125015A3 Method and apparatus for time measurement |
| 12/28/2006 | US20060291604 PLL noise smoothing using dual-modulus interleaving |
| 12/28/2006 | US20060290435 Type-II All-Digital Phase-Locked Loop (PLL) |
| 12/28/2006 | US20060290434 Apparatus, system and method capable of clock noise mitigation using a frequency adaptive process |
| 12/28/2006 | US20060290433 Phase-switching dual modulus prescaler |
| 12/28/2006 | US20060290406 Switched capacitor circuit capable of minimizing clock feedthrough effect and having low phase noise and method thereof |
| 12/28/2006 | US20060290403 Differential clock tree in an integrated circuit |
| 12/28/2006 | US20060290398 BIST to provide jitter data and associated methods of operation |
| 12/28/2006 | US20060290397 Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit |
| 12/28/2006 | US20060290396 Method and apparatus for glitch-free control of a delay-locked loop in a network device |
| 12/28/2006 | US20060290395 Digital DLL device, digital DLL control method, and digital DLL control program |
| 12/28/2006 | US20060290394 Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof |
| 12/28/2006 | US20060290393 Clock generating circuit and clock generating method |
| 12/28/2006 | US20060290392 Clock generators |
| 12/28/2006 | US20060290391 Integrated clock generator with programmable spread spectrum using standard PLL circuitry |
| 12/27/2006 | EP1737174A1 Transmitter circuit, receiver circuit, clock extracting circuit, data transmitting method, and data transmitting system |
| 12/27/2006 | EP1737137A1 Transmitter/receiver for transmitting and receiving of an RF signal in two frequency bands and a method for the same |
| 12/27/2006 | EP1737131A1 Phase locked loop and receiver using the same, phase detecting method |
| 12/27/2006 | EP1736857A2 Communication apparatus and frame display method |
| 12/27/2006 | EP1735910A2 Transconductance and current modulation for resonant frequency control and selection |
| 12/27/2006 | EP1735904A2 Monolithic clock generator and timing/frequency reference |
| 12/27/2006 | EP1444800B1 Digital audio broadcast devices |
| 12/27/2006 | EP1444783B1 Cascaded delay locked loop circuit |
| 12/27/2006 | EP1410510B1 Pll cycle slip compensation |
| 12/27/2006 | EP1188249A4 Spread-spectrum gmsk/m-ary radio with oscillator frequency correction |
| 12/27/2006 | EP1116323B1 Lock-in aid frequency detector |
| 12/27/2006 | CN1885809A Cross interconnection method for RPR and cross site, cross RPR |
| 12/27/2006 | CN1885721A Phase locked loop circuit and method of locking a phase |
| 12/27/2006 | CN1885720A Clock generating circuit and clock generating method |
| 12/26/2006 | US7155191 Method and arrangement for reducing phase jumps when switching between synchronization sources |
| 12/26/2006 | US7155190 DDS-PLL method for frequency sweep |
| 12/26/2006 | US7155188 Integrated circuit and receiving device |
| 12/26/2006 | US7155175 Reduction of parasitic impedances in a phase-locked loop |
| 12/26/2006 | US7155000 Process, arrangement, devices for seizure of a shared telephone line |
| 12/26/2006 | US7154979 Timing recovery with variable bandwidth phase locked loop and non-linear control paths |
| 12/26/2006 | US7154978 Cascaded delay locked loop circuit |
| 12/26/2006 | US7154977 Techniques to reduce transmitted jitter |
| 12/26/2006 | US7154976 Frequency controller |
| 12/26/2006 | US7154352 Clock generator and related biasing circuit |
| 12/26/2006 | US7154348 Frequency synthesizer using a wide-band voltage controlled oscillator and a fast adaptive frequency calibration method |
| 12/26/2006 | US7154347 Compensating method for a PLL circuit that functions according to the two-point principle, and PLL circuit provided with a compensating device |