Patents for H03D 3 - Demodulation of angle-modulated oscillations (6,449)
09/2007
09/04/2007US7266171 Phase-locked loop circuit and radio communication apparatus using the same
09/04/2007US7266170 Signal generating circuit, timing recovery PLL, signal generating system and signal generating method
09/04/2007US7266169 Phase interpolater and applications thereof
09/04/2007US7266163 FSK demodulator slicer with fast automatic DC offset compensation
09/04/2007US7266161 Efficient method and apparatus for parallel processing for use with high-speed single-bit sampling
09/04/2007US7265594 Methods and apparatus for generating timing signals
08/2007
08/30/2007US20070201597 Sub-sampled digital programmable delay locked loop with triangular waveform preshaper
08/30/2007US20070201596 Clock synchronization using early clock
08/30/2007US20070201595 Clock recovery system
08/30/2007US20070201594 Phase Locked Loop (Pll) Circuit, Its Phasing Method And Operation Analyzing Method
08/28/2007US7263153 Clock offset compensator
08/28/2007US7263139 Phase correction for a phase modulated signal with mutually interfering symbols
08/28/2007US7262645 System and method for adjusting the phase of a frequency-locked clock
08/23/2007US20070197176 Fm signal demodulation method and device thereof
08/23/2007US20070195918 Sampling clock generator circuit and data receiver using the same
08/23/2007US20070195917 Phase locked loop circuitry
08/23/2007US20070195916 Synchronous follow-up apparatus and synchronous follow-up method
08/23/2007US20070195913 Phase lock loop and method for coded waveforms
08/23/2007US20070194842 Error correction for vibratory rate gyroscope
08/22/2007CN101023577A Digital noise coupling reduction and variable intermediate frequency generation in mixed signal circuits
08/21/2007US7260168 Network measurement method and apparatus
08/21/2007US7260159 Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying (QPSK) or offset quaternary phase shift keying (OQPSK)
08/21/2007CA2239681C In-phase and quadrature signal regeneration
08/16/2007US20070190957 Dc removal techniques for wireless networking
08/16/2007US20070189431 Delay alignment in a closed loop two-point modulation all digital phase locked loop
08/16/2007US20070189430 Phase-locked loop circuit with a mixed mode loop filter
08/16/2007US20070189429 Low Power Charge Pump
08/16/2007US20070189360 Method and apparatus for generation of asynchronous clock for spread spectrum transmission
08/14/2007US7257379 Compensating for analog radio component impairments to relax specifications
08/14/2007US7257184 Phase comparator, clock data recovery circuit and transceiver circuit
08/14/2007US7257183 Digital clock recovery circuit
08/14/2007US7257178 Base band circuit of receiver and low cut-off frequency control method
08/09/2007US20070183553 Clock and data recovery circuit having gain control
08/09/2007US20070183552 Clock and data recovery circuit including first and second stages
08/08/2007CN1331149C Phase frequency comparing equipment
08/08/2007CN101015120A Thermal-mechanical signal processing
08/07/2007US7254208 Delay line based multiple frequency generator circuits for CDMA processing
08/07/2007US7254187 Narrow band chaotic bi-phase shift keying
08/02/2007US20070177704 Rate locked loop radar timing system
08/02/2007US20070177703 Phase locked loop circuit and information reproduction apparatus
08/02/2007US20070177702 Receiving data over channels with intersymbol interference
08/01/2007EP1812891A2 Apparatus for wavelet modulation by adaptive filter bank
08/01/2007CN101010872A Radio receiver front-end and a method for suppressing out-of-band interference
08/01/2007CN101010871A Receiver and method for wireless communications terminal
08/01/2007CN101009493A Integrated DSP for a DC offset cancellation loop
07/2007
07/31/2007US7251305 Method and apparatus to store delay locked loop biasing parameters
07/31/2007US7251296 System for clock and data recovery
07/26/2007US20070172014 Digital PLL circuit and optical disk apparatus having digital PLL circuit
07/26/2007US20070172013 Frequency-to-current converter
07/26/2007US20070172012 Timing recovery system for a multi-pair gigabit transceiver
07/25/2007EP1811676A1 Fm receiver
07/24/2007US7248664 Timesliced discrete-time phase locked loop
07/24/2007US7248649 Digital baseband receiver including a time domain compensation module for suppressing group delay variation distortion incurred due to analog low pass filter deficiencies
07/19/2007WO2007034420A3 Zero or low if receiver
07/19/2007US20070165764 Phase conjugate circuit
07/19/2007US20070165748 Low if radio receiver
07/18/2007EP1756939A4 Burst mode receiver based on charge pump pll with idle-time loop stabilizer
07/18/2007EP1378090B1 Data capture technique for high speed signaling
07/18/2007CN1327628C System and apparatus for direct conversion receiver and transmitter
07/17/2007US7245897 Using an electroacoustic resonator
07/17/2007US7245894 Radio receiver and radio signal processing method with controlling gain
07/17/2007US7245687 Digital phase-locked loop device for synchronizing signal and method for generating stable synchronous signal
07/17/2007US7245672 Method and apparatus for phase-domain semi-coherent demodulation
07/17/2007CA2319392C Radio receiver that digitizes a received signal at a plurality of digitization frequencies
07/12/2007WO2007079282A2 Dynamic switching of carrier tracking loops without loss of tracking information
07/11/2007EP0947046B1 Dpsk demodulator
07/10/2007US7242741 Delay phase-locked loop device and clock signal generating method
07/10/2007US7242740 Digital phase-locked loop with master-slave modes
07/10/2007US7242739 Method and apparatus for multiphase, fast-locking clock and data recovery
07/10/2007US7242738 Phase detector for a phase-locked loop
07/10/2007US7242730 Mirror suppression circuit and receiver using such circuit
07/10/2007US7242729 Signal decoding method and apparatus
07/05/2007US20070153953 Phase-Locked Loop
07/05/2007US20070153952 Frequency modulated output clock from a digital phase locked loop
07/05/2007US20070153951 Phase interpolation for phase-locked loops
07/05/2007US20070153950 Delay circuit with timing adjustment function
07/05/2007US20070153949 PLL apparatus with power saving mode and method for implementing the same
07/05/2007US20070153941 Method and apparatus for coordinating transmission of short messages with hard handoff searches in a wireless communications system
07/05/2007US20070153880 Dynamic switching of carrier tracking loops without loss of tracking information
07/04/2007EP1803216A2 Sigma-delta based phase lock loop
07/04/2007CN1324604C Oscillating clock generating circuit and method thereof
07/03/2007US7239675 GFSK receiver
07/03/2007CA2245739C Output stage for a low-current charge pump and demodulator integrating such a pump
06/2007
06/28/2007US20070147570 Phase detector for data communications
06/28/2007US20070147569 Transceiver with selectable data rate
06/27/2007EP1801985A2 Method of removing DC offset for a ZIF-based GSM radio receiver with digital frequency offset correction
06/27/2007EP1801963A2 Detecting and correcting I/Q crosstalk in complex quadrature-modulated signals
06/26/2007US7236762 Direct-conversion receiver system and method, especially a GPS receiver system with high pass filtering
06/26/2007US7236556 Synchronising circuit
06/26/2007US7236212 System and method for providing a low power receiver design
06/21/2007US20070142080 Direct-conversion transmitter circuit and transceiver system
06/21/2007US20070140399 Phase-locked loop
06/21/2007US20070140380 Method for the higher order blind demodulation of a linear wave-shaped emitter
06/20/2007EP1500184B1 Dc removal techniques for wireless networking
06/19/2007US7233638 Sampling clock generator circuit and data receiver using the same
06/19/2007US7233637 Wideband communication using delay line clock multiplier
06/19/2007US7233632 Symbol timing correction for a phase modulated signal with mutually interfering symbols
06/19/2007US7233631 DC-offset correction circuit having a DC control loop and a DC blocking circuit
06/14/2007WO2007067606A2 Dc technique for eliminating phase ambiguity in clocking signals
06/14/2007US20070133730 Apparatus and method for avoiding steady-state oscillations in the generation of clock signals
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