Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
Patents for H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate (229,248)
05/1991
05/21/1991US5018102 Memory having selected state on power-up
05/21/1991US5018100 Semiconductor memory device
05/21/1991US5018074 Method of making gate array masks
05/21/1991US5018018 Apparatus for detecting distribution of electric surface potential
05/21/1991US5018000 For preventing malfunction due to alpha-radiation from radioactive material contained in packaging material
05/21/1991US5017997 Integrated circuit with high output current I2 L transistor
05/21/1991US5017996 Semiconductor device and production method thereof
05/21/1991US5017994 Semiconductor circuit
05/21/1991US5017993 Semiconductor integrated circuit device with bus lines
05/21/1991US5017989 Solid state radiation sensor array panel
05/21/1991US5017988 Image reading device with protective layers
05/21/1991US5017987 Contact type image sensor
05/21/1991US5017985 Input protection arrangement for VLSI integrated circuit devices
05/21/1991US5017984 Amorphous silicon thin film transistor array
05/21/1991US5017982 Semiconductor Memory Cells
05/21/1991US5017981 Semiconductor memory and method for fabricating the same
05/21/1991US5017980 Electrically-erasable, electrically-programmable read-only memory cell
05/21/1991US5017979 EEPROM semiconductor memory device
05/21/1991US5017978 EPROM having a reduced number of contacts
05/21/1991US5017977 Dual EPROM cells on trench walls with virtual ground buried bit lines
05/21/1991US5017828 Semiconductors; prevent crosstalk current
05/21/1991US5017807 Output buffer having capacitive drive shunt for reduced noise
05/21/1991US5017515 Process for minimizing lateral distance between elements in an integrated circuit by using sidewall spacers
05/21/1991US5017507 Method of fabricating semiconductor integrated circuit devices including updiffusion to selectively dope a silicon layer
05/21/1991US5017506 Minimization of surface area of memory cell while maintaining adeqate storage capacity
05/21/1991US5017504 Vertical type MOS transistor and method of formation thereof
05/21/1991US5017503 Process for making a bipolar transistor including selective oxidation
05/21/1991US5017502 Laser irradiation cutting grooves; filling with insulating films; forming lead electrode strips diagonally
05/21/1991CA2068991A1 Semi-conductor structures
05/21/1991CA1284393C Catalysts for accelerating burnout of organic materials
05/21/1991CA1284392C Metal-oxide-semiconductor (mos) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit
05/21/1991CA1284391C2 Semiconductor structure with silicide base tap
05/16/1991WO1991006981A1 Mos logic in bicmos circuits
05/16/1991WO1991006980A1 Semiconducteur integrated circuit
05/16/1991WO1991006979A1 Method and device for compensating drift in a semiconductor element
05/16/1991DE4036091A1 Semiconductor DRAM with cell array - has number of groups of memory cells in matrix, each with word lines to energise column and line cells
05/15/1991EP0427565A2 Integrated circuit having MIS transistor
05/15/1991EP0427319A2 Device for the protection against breakdown of an N+ type diffuse region inserted in a vertical-type semiconductor integrated power structure
05/15/1991EP0427284A2 Semiconductor memory device
05/15/1991EP0427255A2 Semiconductor integrated circuit device and the method of manufacturing the same
05/15/1991EP0427253A2 Semiconductor integrated circuit device including bipolar transistors, MOS FETs and CCD
05/15/1991EP0427200A1 Semiconductor memory cell with improved stacked capacitor and process of fabrication thereof
05/15/1991EP0427196A1 Hall IC formed in GaAs substrate
05/15/1991EP0427091A1 Input/output circuit in a semiconductor integrated circuit device
05/15/1991EP0359743B1 Cmos-ram store on a gate array arrangement
05/15/1991CN1051448A Word erasable buried bit line eeprom
05/15/1991CN1051438A Source voltage control circuit
05/14/1991US5016216 Decoder for a floating gate memory
05/14/1991US5016212 IC card having system ROM selection inhibit
05/14/1991US5016108 Solid-state imaging device having series-connected pairs of switching MOS transistors for transferring signal electric charges therethrough
05/14/1991US5016080 Programmable die size continuous array
05/14/1991US5016079 Integrated injection logic gate with heavily doped diffusion
05/14/1991US5016078 CMOS integrated circuit structure protected against electrostatic discharges
05/14/1991US5016077 Insulated gate type semiconductor device and method of manufacturing the same
05/14/1991US5016075 Semiconductor memory device
05/14/1991US5016071 Dynamic memory device
05/14/1991US5016070 Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors
05/14/1991US5016069 Large-scale EPROM memory
05/14/1991US5016068 Vertical floating-gate transistor
05/14/1991US5015889 Schottky enhanced CMOS output circuit
05/14/1991US5015876 High speed charge-coupled sampler and rate reduction circuit
05/14/1991US5015874 Status holding circuit and logic circuit using the same
05/14/1991US5015858 Thermally isolated focal plane readout
05/14/1991US5015838 Color sensor having laminated semiconductor layers
05/14/1991US5015837 Contact type image sensor with electric shielding
05/14/1991US5015601 Method of manufacturing a nonvolatile semiconductor device
05/14/1991US5015599 Method of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions
05/14/1991US5015598 Metal-insulator-smiconductor
05/14/1991US5015597 Process for the production of an inverted structure, active matrix display screen
05/14/1991US5015594 Process of making BiCMOS devices having closely spaced device regions
05/14/1991US5015593 Method of manufacturing semiconductor device
05/14/1991CA1284234C Apparatus including resonant-tunneling device having multiple-peak current-voltage characteristics
05/14/1991CA1284232C Low dose emitter vertical fuse
05/10/1991WO1991007780A1 Semiconductor switch
05/10/1991CA2069911A1 Semiconductor device
05/08/1991EP0426284A1 RF transistor package with nickel oxide barrier
05/08/1991EP0426282A2 Three transistor EEPROM cell
05/08/1991EP0426251A1 Process for manufacturing a device having MIS transistors with an inverted T-shaped gate electrode
05/08/1991EP0426250A1 Process for manufacturing a device having MIS transistors with a gate overlapping the lightly-doped source and drain regions
05/08/1991EP0426241A2 Process for the manufacture of a component to limit the programming voltage and to stabilise the voltage incorporated in an electric device with EEPROM memory cells
05/08/1991EP0426174A2 Semiconductor integrated circuit
05/08/1991EP0426151A2 Method of manufacturing a multi-layered wiring structure of semiconductor integrated circuit device
05/08/1991EP0426103A2 Electronic circuit device for protecting electronic circuits from unwanted removal of ground terminal
05/08/1991EP0425965A2 Method of fabricating semiconductor structures
05/08/1991EP0425776A1 Package for a solid-state imaging device
05/08/1991CN1051277A Mos logic in bicmos circuits
05/07/1991US5014243 Programmable read only memory (PROM) having circular shaped emitter regions
05/07/1991US5014241 Dynamic semiconductor memory device having reduced soft error rate
05/07/1991US5014132 CCD imager
05/07/1991US5014110 Wiring structures for semiconductor memory device
05/07/1991US5014107 Process for fabricating complementary contactless vertical bipolar transistors
05/07/1991US5014106 Semiconductor device for use in a hybrid LSI circuit
05/07/1991US5014105 Semiconductor device of complementary integrated circuit
05/07/1991US5014104 Semiconductor integrated circuit having CMOS inverters
05/07/1991US5014103 Dynamic random access memory having improved layout and method of arranging memory cell pattern of the dynamic random access memory
05/07/1991US5014102 MOSFET-gated bipolar transistors and thyristors with both turn-on and turn-off capability having single-polarity gate input signal
05/07/1991US5014101 Semiconductor IGBT with improved turn-off switching time
05/07/1991US5014100 Image sensor free from undesirable incident light rays which have not been reflected in the surface bearing the image to be sensed
05/07/1991US5014099 Dynamic RAM cell with trench capacitor and trench transistor
05/07/1991US5014098 CMOS integrated circuit with EEPROM and method of manufacture
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