Patents for H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate (229,248) |
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05/15/2001 | US6232639 Method and structure to reduce latch-up using edge implants |
05/15/2001 | US6232638 Semiconductor device and manufacturing method for same |
05/15/2001 | US6232637 Semiconductor fabrication having multi-level transistors and high density interconnect therebetween |
05/15/2001 | US6232635 Method to fabricate a high coupling flash cell with less silicide seam problem |
05/15/2001 | US6232634 Non-volatile memory cell and method for manufacturing same |
05/15/2001 | US6232633 NVRAM cell using sharp tip for tunnel erase |
05/15/2001 | US6232632 Double density non-volatile memory cells |
05/15/2001 | US6232631 Floating gate memory cell structure with programming mechanism outside the read path |
05/15/2001 | US6232629 Ferroelectric capacitor and a method for manufacturing thereof |
05/15/2001 | US6232628 Semiconductor device having stacked capacitor structure |
05/15/2001 | US6232626 Trench photosensor for a CMOS imager |
05/15/2001 | US6232621 Semiconductor device and method of fabricating the same |
05/15/2001 | US6232607 High resolution flat panel for radiation imaging |
05/15/2001 | US6232606 Flat panel detector for radiation imaging and pixel for use therein |
05/15/2001 | US6232591 Light detection device |
05/15/2001 | US6232590 Solid state image sensor and method for fabricating the same |
05/15/2001 | US6232589 Single polysilicon CMOS pixel with extended dynamic range |
05/15/2001 | US6232562 Hybrid integrated circuit device |
05/15/2001 | US6232240 Method for fabricating a capacitor |
05/15/2001 | US6232227 Method for making semiconductor device |
05/15/2001 | US6232225 Method of fabricating contact window of semiconductor device |
05/15/2001 | US6232224 Method of manufacturing semiconductor device having reliable contact structure |
05/15/2001 | US6232206 Method for forming electrostatic discharge (ESD) protection transistors |
05/15/2001 | US6232201 Semiconductor substrate processing method |
05/15/2001 | US6232195 Structure of semiconductor device |
05/15/2001 | US6232194 Silicon nitride capped poly resistor with SAC process |
05/15/2001 | US6232193 Method of forming isolated integrated injection logic gate |
05/15/2001 | US6232190 Method of forming junction diodes |
05/15/2001 | US6232187 Semiconductor device and manufacturing method thereof |
05/15/2001 | US6232182 Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same |
05/15/2001 | US6232181 Method of forming a flash memory |
05/15/2001 | US6232180 Split gate flash memory cell |
05/15/2001 | US6232178 Method for manufacturing capacitive element |
05/15/2001 | US6232173 Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure |
05/15/2001 | US6232172 Method to prevent auto-doping induced threshold voltage shift |
05/15/2001 | US6232169 Method for producing a capacitor |
05/15/2001 | US6232167 Method of producing a ferroelectric thin film coated substrate |
05/15/2001 | US6232163 Method of forming a semiconductor diode with depleted polysilicon gate structure |
05/15/2001 | US6232157 Thin film transistors |
05/15/2001 | US6232156 Method of manufacturing a semiconductor device |
05/15/2001 | US6232155 Methods of fabricating semiconductor-on-insulator devices including alternating thin and thick film semiconductor regions on an insulating layer |
05/15/2001 | US6232154 Optimized decoupling capacitor using lithographic dummy filler |
05/15/2001 | US6232136 Method of transferring semiconductors |
05/15/2001 | US6232133 Method for fabricating a capacitor of semiconductor memory device |
05/15/2001 | CA2101559C Complementary logic input parallel (clip) logic circuit family |
05/10/2001 | WO2001033715A1 On-chip decoupling capacitor system with parallel fuse |
05/10/2001 | WO2001033638A1 Optical semiconductor housing and method for making same |
05/10/2001 | WO2001033634A1 Imager with reduced fet photoresponse and high integrity contact via |
05/10/2001 | WO2001033633A1 Semiconductor memory and method of driving semiconductor memory |
05/10/2001 | WO2001033628A1 A method of forming dual gate oxide layers of varying thickness on a single substrate |
05/10/2001 | WO2001033626A1 Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
05/10/2001 | WO2001033622A1 Solid-source doping for source/drain of flash memory |
05/10/2001 | WO2001033571A1 Flash memory wordline tracking across whole chip |
05/10/2001 | WO2001033293A1 Integrated circuit with opposed spatial light modulator and processor |
05/10/2001 | WO2001033238A1 A scan test point observation system and method |
05/10/2001 | WO2001017019A3 Memory with a trench capacitor and a selection transistor and method for producing the same |
05/10/2001 | WO2001006577A8 Cavity-emission electroluminescent device and method for forming the device |
05/10/2001 | WO2000041459A3 Semiconductor element with a tungsten oxide layer and method for its production |
05/10/2001 | US20010001076 Semiconductor device with no step between well regions |
05/10/2001 | US20010001073 Semiconductor device and method for forming the same |
05/10/2001 | US20010001072 Body-potential drawing region can draw and fix a body potential |
05/10/2001 | US20010001050 Method of manufacturing organic EL element, organic EL element, and organic EL display device |
05/10/2001 | US20010001045 Substrate for high frequency integrated circuits |
05/10/2001 | US20010000993 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield |
05/10/2001 | US20010000991 Semiconductor memory device |
05/10/2001 | US20010000990 Semiconductor memory device |
05/10/2001 | US20010000943 Organic electroluminescence device and method of manufacturing same |
05/10/2001 | US20010000926 Method and materials for through-mask electroplating and selective base removal |
05/10/2001 | US20010000923 Thin film capacitor having an improved bottom electrode and method of forming the same |
05/10/2001 | US20010000922 Semiconductor device having semiconductor regions of different conductivity types isolated by field oxide, and method of manufacturing the same |
05/10/2001 | US20010000921 Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits |
05/10/2001 | DE19943405A1 Verfahren zur Herstellung eines lateral monolithisch integrierten Lichtemissions-Halbleiterbauelements A process for preparing a laterally monolithically integrated light emitting semiconductor component |
05/10/2001 | DE10055450A1 Capacitor for semiconductor memory such as DRAM has silicon nitride film formed between lower electrode and tantalum oxide film on which upper electrode is formed |
05/10/2001 | DE10053417A1 Image scanner e.g. for medical use has cover over scintillator sealed to substrate and enclosed by U=shaped cap |
05/10/2001 | DE10046910A1 Semiconductor device comprises a lower layer with a main surface and a capacitor formed on the main surface of the lower layer |
05/10/2001 | DE10046021A1 Capacitor production on a substrate by forming a lower electrode on the substrate, forming a dielectric layer on the electrode, oxygen radical or plasma heat treating the dielectric layer and forming the upper electrode |
05/10/2001 | DE10037973A1 Data output circuit has buffer stage containing pull-up and pull-down transistors, high and low level data output control stages and substrate potential switching stage |
05/10/2001 | DE10019805A1 Dynamische Halbleiterspeichervorrichtung mit reduziertem Stromverbrauch im Lesebetrieb Dynamic semiconductor memory device with reduced power consumption in the reading operation |
05/10/2001 | DE10019708A1 Semiconductor device comprises a region of a first conducting type formed on the surface of a semiconductor substrate, an element-forming region, a semiconductor element, an insulation film and a contact hole |
05/09/2001 | EP1098512A2 Pixel design for interlaced reading for high sensitivity CMOS image sensors |
05/09/2001 | EP1098376A2 Organic EL device and image-reading, data-processing and display apparatus including the device |
05/09/2001 | EP1098373A2 A semiconductor light source |
05/09/2001 | EP1098370A2 DRAM cell array and method of making the same |
05/09/2001 | EP1098358A2 Method for making field effect devices and capacitors with thin film dielectrics and resulting devices |
05/09/2001 | EP1098324A2 Ferroelectric non-volatile latch circuits |
05/09/2001 | EP1098259A2 Rate equation method and apparatus for simulation of current in a mos device |
05/09/2001 | EP1097569A1 Sensor matrix |
05/09/2001 | EP1097483A2 Device for detecting electromagnetic radiation |
05/09/2001 | EP1097471A1 Integrated circuit with at least one transistor and a capacitor and corresponding production method |
05/09/2001 | EP1097458A1 Storage assembly consisting of resistive ferroelectric storage cells |
05/09/2001 | EP1097457A2 Storage cell system in which an electric resistance of a storage element represents an information unit and can be influenced by a magnetic field, and method for producing same |
05/09/2001 | EP1097456A1 Universal memory element and method of programming same |
05/09/2001 | EP1044452A4 Programmable sub-surface aggregating metallization structure and method of making same |
05/09/2001 | CN1294783A Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit |
05/09/2001 | CN1294759A Memory unit device and its mfg. method |
05/09/2001 | CN1294757A Inductance device |
05/09/2001 | CN1294755A Method for generating electrical conducting or semiconducting structures in two or three dimensions, method for erasing same structures and electric field generator/modulator |
05/09/2001 | CN1294390A Field response reinforced magnetic component and its mfg. method |
05/09/2001 | CN1065658C Method for fabricating capacitor of semiconductor device and capacitor |
05/08/2001 | US6230300 Method and apparatus for the optimization of a tree depth for clock distribution in semiconductor integrated circuits |