Patents
Patents for H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate (229,248)
07/2001
07/11/2001EP1114462A1 Ternary nitride-carbide barrier layers
07/11/2001EP1114461A1 Semiconductor circuit
07/11/2001EP1114460A1 Semiconductor chip with surface coating
07/11/2001EP1114459A1 High voltage shield
07/11/2001EP1114458A1 Buried local interconnect
07/11/2001EP1114455A1 Method for producing a storage cell
07/11/2001EP1114454A2 Silicon on insulator structure from low defect density single crystal silicon
07/11/2001EP1114451A1 Microelectronic structure, production method and utilization of the same
07/11/2001EP1114449A1 Ruthenium silicide diffusion barrier layers and methods of forming same
07/11/2001EP1114448A1 A method of manufacturing a semiconductor device
07/11/2001EP1114446A1 Method for producing a thin membrane and resulting structure with membrane
07/11/2001EP1114443A1 Voltage-cycling recovery of process-damaged ferroelectric films
07/11/2001CN1303228A Luminescence display apparatus and its manufacturing method
07/11/2001CN1303132A MIM capacitor
07/11/2001CN1303129A Method of epitaxial bipolar device and complementary metallic oxide semiconductor device
07/11/2001CN1303128A Manufacturing method of ferroelectric semi conductor storage
07/11/2001CN1303127A Non volatile semi-conductor memory and its manufacturing method
07/11/2001CN1303126A Equivalent circuit for simulating ferroelectric capacitance
07/11/2001CN1303098A MTJ stack type unit storage detecting method and device
07/11/2001CN1303069A Contact type image sensor possessing light guiding device
07/11/2001CN1068459C Static random access storage and its manufacturing method
07/10/2001US6260181 Integrated circuit and the design method thereof
07/10/2001US6259846 Light-emitting fiber, as for a display
07/10/2001US6259644 Equipotential sense methods for resistive cross point memory cell arrays
07/10/2001US6259636 Semiconductor memory device having redundancy circuit for relieving faulty memory cells
07/10/2001US6259612 Semiconductor device
07/10/2001US6259423 Display device using organic electroluminescent elements
07/10/2001US6259309 Method and apparatus for the replacement of non-operational metal lines in DRAMS
07/10/2001US6259307 Temperature compensated voltage gain stage
07/10/2001US6259291 Self-adjusting apparatus and a self-adjusting method for adjusting an internal oscillating clock signal by using same
07/10/2001US6259151 Use of barrier refractive or anti-reflective layer to improve laser trim characteristics of thin film resistors
07/10/2001US6259150 Voltage dividing resistor and voltage dividing circuit
07/10/2001US6259148 Modular high frequency integrated circuit structure
07/10/2001US6259145 Reduced leakage trench isolation
07/10/2001US6259143 Semiconductor memory device of NOR type mask ROM and manufacturing method of the same
07/10/2001US6259140 Silicide blocking process to form non-silicided regions on MOS devices
07/10/2001US6259139 Embedded well diode MOS ESD protection circuit
07/10/2001US6259138 Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
07/10/2001US6259136 High-breakdown-voltage semiconductor device
07/10/2001US6259135 MOS transistors structure for reducing the size of pitch limited circuits
07/10/2001US6259134 Trench thyristor with improved breakdown voltage characteristics
07/10/2001US6259133 Method for forming an integrated circuit memory cell and product thereof
07/10/2001US6259132 Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cells
07/10/2001US6259126 Low cost mixed memory integration with FERAM
07/10/2001US6259124 Active pixel sensor with high fill factor blooming protection
07/10/2001US6259119 Liquid crystal display and method of manufacturing the same
07/10/2001US6259116 Multiple memory element semiconductor memory devices
07/10/2001US6259085 Fully depleted back illuminated CCD
07/10/2001US6259083 Solid state imaging device and manufacturing method thereof
07/10/2001US6258727 Method of forming metal lands at the M0 level with a non selective chemistry
07/10/2001US6258722 Method of manufacturing CMOS device
07/10/2001US6258708 Method of fabricating gate contact pods, load lines and wiring structures using a minimum number of etching steps
07/10/2001US6258698 Process for producing semiconductor substrate
07/10/2001US6258691 Cylindrical capacitor and method for fabricating same
07/10/2001US6258690 Method of manufacturing semiconductor device
07/10/2001US6258688 Method to form a high Q inductor
07/10/2001US6258684 Method of fabricating semiconductor memory device having a soi structure
07/10/2001US6258672 Method of fabricating an ESD protection device
07/10/2001US6258671 Methods of providing spacers over conductive line sidewalls, methods of forming sidewall spacers over etched line sidewalls, and methods of forming conductive lines
07/10/2001US6258669 Methods and arrangements for improved formation of control and floating gates in non-volatile memory semiconductor devices
07/10/2001US6258668 Array architecture and process flow of nonvolatile memory devices for mass storage applications
07/10/2001US6258665 Non-volatile semiconductor memory device and method for manufacturing the same
07/10/2001US6258662 Method for forming cylindrical DRAM capacitors
07/10/2001US6258659 Embedded vertical DRAM cells and dual workfunction logic gates
07/10/2001US6258658 Memory cell configuration and corresponding fabrication method
07/10/2001US6258656 Capacitor with high-ε dielectric or ferroelectric material based on the fin stack principle and production process using a negative mold
07/10/2001US6258654 Method of manufacturing a semiconductor device
07/10/2001US6258650 Method for manufacturing semiconductor memory device
07/10/2001US6258649 Semiconductor integrated circuit device and method of manufacturing the same
07/10/2001US6258646 CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof
07/10/2001US6258644 Mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps
07/10/2001US6258642 Use of functional memory cells as guard cells in a semiconductor memory
07/10/2001US6258641 OTP (open trigger path) latchup scheme using triple and buried well for sub-quarter micron transistors
07/10/2001US6258640 Semiconductor device manufacturing method
07/10/2001US6258638 Method of manufacturing thin film transistor
07/10/2001US6258636 SOI active pixel cell design with grounded body contact
07/10/2001US6258634 Method for manufacturing a dual-direction over-voltage and over-current IC protection device and its cell structure
07/10/2001US6258319 Device and method for photoactivation
07/10/2001US6258240 Anodizing apparatus and method
07/10/2001US6257739 Scanning vertical cavity surface emitting laser array capable of page-width image scan
07/10/2001CA2203489C Circuit in cmos technology for high speed driving of optical sources
07/05/2001WO2001049044A2 Method for temperature compensation of an image sensor sensitivity
07/05/2001WO2001048828A1 L- and u-gate devices for soi/sos applications
07/05/2001WO2001048827A1 A semiconductor device
07/05/2001WO2001048826A1 Semiconductor energy sensor
07/05/2001WO2001048824A1 High-voltage capacitor voltage divider circuit having a high-voltage silicon-on-insulator (soi) capacitor
07/05/2001WO2001048823A1 An integrated circuit with metal programmable logic having enhanced reliability
07/05/2001WO2001048822A2 Thin-film transistor circuitry
07/05/2001WO2001048814A1 Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer
07/05/2001WO2001048493A2 Low power scan flipflop
07/05/2001WO2001047720A1 Thermal mass transfer donor element with light-to-heat conversion layer
07/05/2001WO2001011673A3 Method for etching oxide films containing bismuth
07/05/2001WO2001001449A3 Semiconductor device manufacturing using low energy high tilt angle ion implantation
07/05/2001WO2000067301A3 Method of making shallow junction semiconductor devices
07/05/2001US20010007151 Fully integrated tuner architecture
07/05/2001US20010007144 Hold violation improvement method, semiconductor integrated circuit, and program for executing hold violation improvement method by computer
07/05/2001US20010007143 Circuit simulation device for predicting the dispersion of circuit characteristics and the electric characteristics
07/05/2001US20010007091 Integrated circuit provided with means for calibrating an electronic module and method for calibrating an electronic module of an integrated circuit
07/05/2001US20010006838 Methods of forming ruthenium film by changing process conditions during chemical vapor deposition and ruthenium films formed thereby
07/05/2001US20010006837 Forming carbon over active matrix; patterning