Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
Patents for H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate (229,248)
05/2003
05/13/2003US6563182 Semiconductor device and manufacturing method thereof
05/13/2003US6563181 High frequency signal isolation in a semiconductor device
05/13/2003US6563180 Semiconductor integrated circuit device
05/13/2003US6563178 Semiconductor device and method for fabricating the device
05/13/2003US6563177 Semiconductor memory device having a trench and a gate electrode vertically formed on a wall of the trench
05/13/2003US6563176 Integrated circuits; non-self-aligned resistor well compensating implant formed under source; dopes
05/13/2003US6563175 NMOS ESD protection device with thin silicide and methods for making same
05/13/2003US6563174 Thin film transistor and matrix display device
05/13/2003US6563173 Silicon-on-insulator chip having an isolation barrier for reliability
05/13/2003US6563172 Semiconductor substrate processing method
05/13/2003US6563171 High-voltage transistor with buried conduction layer
05/13/2003US6563168 Non-volatile semiconductor device with anti-punch through regions
05/13/2003US6563167 Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges
05/13/2003US6563166 Flash cell device
05/13/2003US6563165 Non-volatile semiconductor memory device and method for producing the same
05/13/2003US6563164 Compositionally modified resistive electrode
05/13/2003US6563160 High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits
05/13/2003US6563159 Substrate of semiconductor integrated circuit
05/13/2003US6563158 Method and apparatus for voltage stiffening in an integrated circuit
05/13/2003US6563157 Semiconductor device having rigid capacitor structure with a liner film
05/13/2003US6563156 Memory elements and methods for making same
05/13/2003US6563155 Cross point type DRAM cell composed of a pillar having an active region
05/13/2003US6563154 Polysilicon layer having improved roughness after POCl3 doping
05/13/2003US6563149 Solid-state imaging device
05/13/2003US6563143 CMOS circuit of GaAs/Ge on Si substrate
05/13/2003US6563141 Optical devices
05/13/2003US6563138 Low-cost, high-density light-emitting-diode array and fabrication method thereof
05/13/2003US6563136 Thin-film semiconductor device having a thin-film transistor for circuits that differs from a thin-film transistor for pixels
05/13/2003US6563135 Thin film transistor and a method of forming the same
05/13/2003US6563124 Electron beam apparatus having traversing circuit boards
05/13/2003US6563118 Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
05/13/2003US6562714 Consolidation method of junction contact etch for below 150 nanometer deep trench-based DRAM devices
05/13/2003US6562704 Method for manufacturing semiconductor device, and semiconductor device
05/13/2003US6562694 Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer
05/13/2003US6562689 Non-ion-implanted resistive silicon oxynitride films as resistors
05/13/2003US6562686 Method for fabricating semiconductor device
05/13/2003US6562683 Bit-line oxidation by removing ONO oxide prior to bit-line implant
05/13/2003US6562681 Nonvolatile memories with floating gate spacers, and methods of fabrication
05/13/2003US6562680 Semiconductor device and method of manufacturing the same
05/13/2003US6562679 Method for forming a storage node of a capacitor
05/13/2003US6562678 Chemical vapor deposition process for fabricating layered superlattice materials
05/13/2003US6562676 Method of forming differential spacers for individual optimization of n-channel and p-channel transistors
05/13/2003US6562673 Method of fabricating a self-aligned split gate flash memory cell
05/13/2003US6562671 Semiconductor display device and manufacturing method thereof
05/13/2003US6562669 Semiconductor device and method of manufacturing the same
05/13/2003US6562666 Integrated circuits with reduced substrate capacitance
05/13/2003US6562664 Method for installing protective components in integrated circuits that are constructed from standard cells
05/13/2003US6562651 Method of manufacturing a semiconductor device having contact pads
05/13/2003US6562634 Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same
05/13/2003US6562633 Assembling arrays of small particles using an atomic force microscope to define ferroelectric domains
05/13/2003US6562548 Overcoating substrate with oxide; doping; heat treatment
05/13/2003US6561839 Process for forming shallow isolating regions in an integrated circuit and an integrated circuit thus formed
05/13/2003US6561693 Remote temperature sensing long wave length modulated focal plane array
05/08/2003WO2003039203A1 Display
05/08/2003WO2003038956A1 Production method for semiconductor light emitting element
05/08/2003WO2003038922A1 Method for applying mechanically sensitive layers to a substrate over a large area
05/08/2003WO2003038921A1 Insulator for an organic electronic component
05/08/2003WO2003038908A2 Method for producing a photodiode contact for a tfa image sensor
05/08/2003WO2003038907A1 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
05/08/2003WO2003038902A2 Broad spectrum light emitting devices and method for fabricating the same
05/08/2003WO2003038901A1 Method for producing a tfa image sensor and one such tfa image sensor
05/08/2003WO2003038900A1 Image displaying method and image displaying device
05/08/2003WO2003038899A2 Semiconductor structure with a coil underneath the first wiring layer or between two wiring layers
05/08/2003WO2003038898A2 Organic electroluminescent display
05/08/2003WO2003038897A2 Electronic unit, circuit design for the same, and production method
05/08/2003WO2003038893A2 Semiconductor structure and method for the production thereof
05/08/2003WO2003038890A2 Method for planarization etch with in-situ monitoring by interferometry prior to recess etch
05/08/2003WO2003038873A2 Removing an amorphous oxide from a monocrystalline surface
05/08/2003WO2003038867A1 Method of manufacturing modules with an organic integrated circuit
05/08/2003WO2003038864A2 Magneto-resistive bit structure and method of manufacturing therefor
05/08/2003WO2003038863A2 Trench dmos device with improved drain contact
05/08/2003WO2003038473A2 Position sensitive solid state detector with internal gain
05/08/2003WO2003021340A3 Optoelectronic displays
05/08/2003WO2002103388A3 Laminated semiconductor radiation detector
05/08/2003US20030088849 Semiconductor integrated circuit device and method for designing the same
05/08/2003US20030088836 Low power test circuit and a semiconductor integrated circuit with the low power test circuit
05/08/2003US20030088785 ID installable LSI, secret key installation method, LSI test method, and LSI development method
05/08/2003US20030087519 Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with a line configuration and method for fabricating a line configuration
05/08/2003US20030087517 A new consolidation method of junction contact etch for below 150 nanometer deep trench-based dram devices
05/08/2003US20030087513 Method for manufacturing semiconductor device
05/08/2003US20030087512 Method of manufacturing a semiconductor device
05/08/2003US20030087509 Method of making semiconductor device
05/08/2003US20030087504 Active wafer cooling during damage engineering implant to enchance buried oxide formation in simox wafers
05/08/2003US20030087501 Capacitor and method of manufacturing the same
05/08/2003US20030087500 Ferroelectric memory device
05/08/2003US20030087499 Process for forming metallized contacts to periphery transistors
05/08/2003US20030087496 Integrated circuit with a MOS capacitor
05/08/2003US20030087491 Simultaneous formation of bottom electrodes and their respective openings of capacitors in both a memory cell region and logic region
05/08/2003US20030087489 Semiconductor integrated circuit device
05/08/2003US20030087486 Integrated semiconductor light sensor device and corresponding manufacturing process
05/08/2003US20030087480 Ferroelectric memory device and method of making the same
05/08/2003US20030087474 Method of manufacturing modules with an integrated circuit
05/08/2003US20030087466 Phototransistor device
05/08/2003US20030087195 Applying electroconductive polymer; masking; exposure to radiation; etching
05/08/2003US20030087026 Multi-nozzle printing method for PLED displays
05/08/2003US20030086321 Methods of increasing write selectivity in an MRAM
05/08/2003US20030086313 Magnetic memory device using SOI substrate and method of manufacturing the same
05/08/2003US20030086308 Semiconductor memory device having a trench capacitor and a manufacturing method thereof
05/08/2003US20030086296 Method of forming and operating trench split gate non-volatile flash memory cell structure
05/08/2003US20030086290 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system
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