Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2014
12/02/2014US8902664 Semiconductor memory device
12/02/2014US8902659 Shared-bit-line bit line setup scheme
12/02/2014US8902655 Nonvolatile memory device providing negative voltage
12/02/2014US8902633 Resistive memory device comprising selectively disabled write driver
12/02/2014US8902627 RFID IC with tunneling-voltage profile calibration
12/02/2014US8901975 Digital PLL with dynamic loop gain control
12/02/2014US8901966 Sensor circuit
12/02/2014US8901956 Configuration context switcher
11/2014
11/27/2014US20140351565 System and apparatus for group floating-point inflate and deflate operations
11/27/2014US20140351502 Method and apparatus for sending data from multiple sources over a communications bus
11/27/2014US20140347945 Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods
11/27/2014US20140347942 Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device
11/27/2014US20140347941 Low latency synchronization scheme for mesochronous ddr system
11/27/2014US20140347939 Semiconductor devices including pipe latch units and system including the same
11/25/2014US8898439 Serial flash memory and address transmission method thereof
11/25/2014US8898377 Semiconductor device and method of generating random data
11/25/2014US8898374 Flash memory device and method for managing flash memory device
11/25/2014US8897093 Controlling method of connector, connector, and memory storage device
11/25/2014US8897090 Memory system having a plurality of serially connected devices
11/25/2014US8897087 Memory device and operating method of memory device and memory system
11/25/2014US8897086 Method and apparatus for memory fault tolerance
11/25/2014US8897085 Immunity against temporary and short power drops in non-volatile memory: pausing techniques
11/25/2014US8897084 Dynamic data strobe detection
11/25/2014US8897083 Memory interface circuitry with data strobe signal sharing capabilities
11/25/2014US8897082 Data transmission circuit and semiconductor memory device including the same
11/25/2014US8897081 Semiconductor memory device
11/25/2014US8897080 Variable rate serial to parallel shift register
11/25/2014US8897064 Compensation scheme for non-volatile memory
11/25/2014US8897055 Memory device, method of operating the same, and electronic device having the memory device
11/25/2014US8897054 ROM device with keepers
11/25/2014US8897053 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
11/25/2014US8897052 Memory architecture
11/25/2014US8897051 Semiconductor storage device and method for producing the same
11/25/2014US8896357 Integrated processor and CDR circuit
11/25/2014US8896348 Semiconductor apparatus
11/20/2014US20140344598 Enabling A Non-Core Domain To Control Memory Bandwidth
11/20/2014US20140344546 Memory Controller For Micro-Threaded Memory Operations
11/20/2014US20140344544 Marching Memory, A Bidirectional Marching Memory, A complex Marching Memory And A Computer System, Without The Memory Bottleneck
11/20/2014US20140344515 Multi-granularity parallel storage system
11/20/2014US20140343930 Systems and Methods for Voice Data Processing
11/20/2014US20140340974 Apparatus and method for writing data into storage of electronic device
11/20/2014US20140340973 Semiconductor device having pda function
11/20/2014US20140340970 Memory with dynamic feedback control circuit
11/20/2014US20140340969 Semiconductor apparatus
11/20/2014US20140340968 Semiconductor integrated circuit
11/20/2014US20140340962 Thyristor memory and methods of operation
11/20/2014US20140340953 Semiconductor device
11/18/2014US8892966 Methods and apparatus for soft data generation for memory devices using decoder performance feedback
11/18/2014US8892825 Method and system for improving serial port memory communication latency and reliability
11/18/2014US8891330 Method and apparatus for simultaneously accessing a plurality of memory cells in a memory array to perform a read operation and/or a write operation
11/18/2014US8891329 Input buffer
11/18/2014US8891328 Low voltage metal gate antifuse with depletion mode MOSFET
11/18/2014US8891327 Semiconductor memory apparatus
11/18/2014US8891326 Method of sensing data in magnetic random access memory with overlap of high and low resistance distributions
11/18/2014US8891324 Memory device from which dummy edge memory block is removed
11/18/2014US8891323 Semiconductor memory device capable of measuring write current and method for measuring write current
11/18/2014US8891321 Outputting a particular data quantization from memory
11/18/2014US8891320 Semiconductor memory apparatus, and divisional program control circuit and program method therefor
11/18/2014US8891319 Verify or read pulse for phase change memory and switch
11/18/2014US8891318 Semiconductor device having level shift circuit
11/18/2014US8891317 Volatile memory with a decreased consumption
11/18/2014US8891313 Memory device and read operation method thereof
11/18/2014US8891302 Electronic equipment
11/18/2014US8891297 Memory cell sensing
11/18/2014US8891295 Semiconductor device
11/18/2014US8891281 Programmable LSI
11/18/2014US8891276 Memory array with local bitlines and local-to-global bitline pass gates and gain stages
11/18/2014US8890576 Input/output sense amplifier
11/13/2014US20140337645 Fast-wake memory
11/13/2014US20140337570 Memory system and method using stacked memory device dice, and system using the memory system
11/13/2014US20140334243 Write level training using dual frequencies in a double data-rate memory device interface
11/13/2014US20140334239 I/o circuit with phase mixer for slew rate control
11/13/2014US20140334238 Low Power Memory Device
11/13/2014US20140334237 Apparatuses, devices and methods for sensing a snapback event in a circuit
11/13/2014US20140334235 Memory macro configuration and method
11/11/2014US8886893 Semiconductor device
11/11/2014US8886892 Memory module and method employing a multiplexer to replace a memory device
11/11/2014US8886180 Enhanced techniques for using core based nodes for state transfer
11/11/2014US8885438 Startup circuit detecting stable system clock
11/11/2014US8885437 Storage device and driving method thereof
11/11/2014US8885436 Semiconductor memory device and method of driving the same
11/11/2014US8885434 Retention of data during stand-by mode
11/11/2014US8885433 Semiconductor device having fuse circuit
11/11/2014US8885432 Semiconductor device that performs refresh operation
11/11/2014US8885431 Semiconductor device changing an active time-out time interval
11/11/2014US8885430 Semiconductor memory device and data processing system
11/11/2014US8885429 Memory device and a method for erasing data stored in the memory device
11/11/2014US8885428 Smart read scheme for memory array sensing
11/11/2014US8885427 Precharge circuit and non-volatile memory device
11/11/2014US8885425 Semiconductor memory and method of controlling the same
11/11/2014US8885424 Integrated circuit and memory device
11/11/2014US8885423 DRAM sense amplifier that supports low memory-cell capacitance
11/11/2014US8885422 Hierarchical on-chip memory
11/11/2014US8885421 Semiconductor memory device
11/11/2014US8885408 Nonvolatile semiconductor memory device for rendering the same in a busy state after inputting data therein
11/11/2014US8885401 Load and short current measurement by current summation technique
11/11/2014US8885400 Compensation scheme for non-volatile memory
11/11/2014US8885394 Semiconductor device with complementary global bit lines, operating method, and memory system
11/11/2014US8885393 Memory array voltage source controller for retention and write assist
11/11/2014US8885380 Semiconductor memory device
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