Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
11/1996
11/26/1996US5579484 System for performing fast data accessing in multiply/accumulate operations while using a VRAM
11/26/1996US5579481 System and method for controlling data transfer between multiple interconnected computer systems with an untethered stylus
11/26/1996US5579453 Smart direct memory access controller
11/26/1996US5579348 Method and apparatus for improving the apparent accuracy of a data receiver clock circuit
11/26/1996US5579315 Heartbeat collision prevention circuit and method
11/26/1996US5579087 Constructing a multi-segment print job from multiple local or remote sources using a network interface
11/26/1996US5578940 Modular bus with single or double parallel termination
11/24/1996CA2177105A1 Information processing system for selectively connecting multiple types of extension devices to connection ports
11/21/1996WO1996036912A2 Address and data bus arbiter for pipelined transactions on a split bus
11/21/1996DE19619497A1 Impulsmodusendeerkennungseinheit Pulse mode end detection unit
11/20/1996EP0743815A2 Segmented shielding structure for connector panels
11/20/1996EP0743777A2 System for packet filtering of data packets at a computer network interface
11/20/1996EP0743597A1 Programming memory devices through the parallel port of a computer system
11/20/1996EP0743595A2 Communication system with means for software exchange
11/20/1996EP0743591A1 Printing system comprising a communication control apparatus
11/20/1996EP0742920A1 Communications architecture and buffer for distributing information services
11/20/1996EP0312615B1 Method and apparatus for data transfer
11/20/1996CN1135931A Communication system and relay thereof
11/19/1996US5577260 Data processing system having a serial interface comprising an end-of-transmission flag
11/19/1996US5577255 Method for transmitting information present at a plurality of data interfaces of a processor-controlled equipment to the processing device thereof
11/19/1996US5577251 Object oriented system for executing application call by using plurality of client-side subcontract mechanism associated with corresponding plurality of server-side subcontract mechanism
11/19/1996US5577237 Protocol timer and method of using same
11/19/1996US5577236 Memory controller for reading data from synchronous RAM
11/19/1996US5577234 System for controlling storage device for storing data at second density that is not integral multiple of first density by varying the device motor speed
11/19/1996US5577230 Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch
11/19/1996US5577229 Computer system and method for pipelined transfer of data between modules utilizing a shared memory and a pipeline having a plurality of registers
11/19/1996US5577215 Data transmission circuit for digital signal processor chip and method therefor
11/19/1996US5577214 Programmable hold delay
11/19/1996US5577213 Multi-device adapter card for computer
11/19/1996US5577211 System and method using chained structure queues for ordering of message delivery between connected nodes wherein unsuccessful message portion is skipped and retried
11/19/1996US5577207 System and method for connecting SCSI units spaced at distance which is greater than the standard maximum length value of the SCSI protocol
11/19/1996US5577206 System for physical layer controllers for performing automatic hardware based scrubbing of input and output dirty flags for updating system configuration changes
11/19/1996US5577205 Chassis for a multiple computer system
11/19/1996US5577204 Parallel processing computer system interconnections utilizing unidirectional communication links with separate request and response lines for direct communication or using a crossbar switching device
11/19/1996US5577041 Method of controlling a personal communication system
11/19/1996US5577005 Circuit for using chip information
11/19/1996US5576554 Wafer-scale integrated circuit interconnect structure architecture
11/19/1996CA2082078C Configurable, recoverable parallel bus
11/17/1996CA2176638A1 Segmented shielding structure for connector panels
11/14/1996WO1996036142A1 System for electronic messaging via wireless devices
11/14/1996WO1996036141A1 A method and an equipment for transmitting a file-based multimedia and hypermedia service to a mobile receiver
11/14/1996WO1996035996A1 Master oriented buffer
11/14/1996WO1996035994A1 Rules based electronic message management system
11/14/1996WO1996035993A2 Method and apparatus for consolidated buffer handling for computer device input/output
11/14/1996WO1996035988A1 Bridge router for high performance scalable networking
11/14/1996DE19615956A1 DRAM connected non-volatile semiconductor memory device
11/13/1996EP0742671A1 Apparatus for fault-tolerant multimedia program distribution
11/13/1996EP0742666A2 Information retrieval device and method
11/13/1996EP0742612A2 Multi-connector termination method and apparatus
11/13/1996EP0742522A1 Processor interrupt control
11/13/1996EP0742521A1 Interrupt control device of small hardware size which deals with much interrupt processing flexibility
11/13/1996EP0742514A1 Method of checking the execution status of a macro
11/13/1996EP0741939A1 Networking module and method for fault-tolerant transmission of system management information
11/13/1996EP0741938A1 Distributed chassis agent for network management
11/13/1996EP0741937A1 Network having secure fast packet switching and guaranteed quality of service
11/12/1996US5574965 Local communication bus system and apparatuses for use in such a system
11/12/1996US5574951 System for providing a time division random access including a high speed unidirectional bus and a plurality of function cards connected in a daisy chain
11/12/1996US5574950 Remote data shadowing using a multimode interface to dynamically reconfigure control link-level and communication link-level
11/12/1996US5574949 Multi-access local area network using a standard protocol for transmitting MIDI data using a specific data frame protocol
11/12/1996US5574948 Method for separating jumpless add-on cards having identical I/O port onto different I/O ports by using comparison technique based on the card numbers
11/12/1996US5574947 Data communication cable for a data terminal for simultaneously connecting multiple peripheral devices and selecting the peripheral devices based on data rate
11/12/1996US5574946 Data transmission system using independent adaptation processes associated with storage unit types for directly converting operating system requests to SCSI commands
11/12/1996US5574944 System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
11/12/1996US5574938 Allowed operational-link transceiver table verifies the operational status of transceivers in a multiple conductor data transmission link
11/12/1996US5574930 Computer system and method using functional memory
11/12/1996US5574929 Processor circuit comprising a first processor, a memory and a peripheral circuit, and system comprising the processor circuit and a second processor
11/12/1996US5574923 Method and apparatus for performing bi-endian byte and short accesses in a single-endian microprocessor
11/12/1996US5574921 Method and apparatus for reducing bus noise and power consumption
11/12/1996US5574885 Modular buffer memory with separately controllable logical output queues for use in packet switched networks
11/12/1996US5574869 Bus bridge circuit having configuration space enable register for controlling transition between various modes by writing the bridge identifier into CSE register
11/12/1996US5574868 Bus grant prediction technique for a split transaction bus in a multiprocessor computer system
11/12/1996US5574866 Method and apparatus for providing a data write signal with a programmable duration
11/12/1996US5574864 Method of implementing EISA bus devices on a host bus by disabling bridge circuitry between host and EISA buses
11/12/1996US5574849 Synchronized data transmission between elements of a processing system
11/12/1996US5574725 Communication method between a personal computer and communication module
11/12/1996CA2066011C Interruption circuit operable at a high speed
11/07/1996WO1996035286A1 Data adapter
11/07/1996WO1996035178A1 Source synchronous clocked data link
11/07/1996WO1996035177A1 A modular system utilizing interchangeable processor cards
11/07/1996WO1996035176A1 Bus bridge address translator
11/07/1996WO1996035175A2 Deadlock avoidance in a split-bus computer system
11/07/1996WO1996035174A2 Bus transaction reordering using side-band information signals
11/07/1996WO1996035173A1 Arbitration of computer resource access requests
11/07/1996WO1996035172A1 Controller for providing access to a video frame buffer in a split-bus transaction environment
11/07/1996WO1996035171A1 Method and apparatus for handling i/o requests
11/07/1996WO1996035170A1 Dynamic device matching using driver candidate lists
11/07/1996DE19523793C1 Stacking memory card connected to bus system
11/07/1996DE19515384A1 Transmission access control circuit for data bus network
11/06/1996EP0741358A2 Microcomputer
11/06/1996EP0741357A2 Distributed computing environment
11/06/1996EP0740874A1 TRANSPARENT INTERCONNECTOR OF LANs BY AN ATM NETWORK
11/06/1996EP0667972B1 Collaborative work system
11/06/1996EP0650617B1 Modem for communicating with enclosed electronic equipment
11/06/1996CN1135058A Information processing unit, device and method
11/05/1996US5572736 Data encoder circuit
11/05/1996US5572734 Method and apparatus for locking arbitration on a remote bus
11/05/1996US5572724 System for controlling communications between an application and a remote system using a protocol identifier and an application context identifier
11/05/1996US5572722 Time skewing arrangement for operating random access memory in synchronism with a data processor
11/05/1996US5572711 Mechanism for linking together the files of emulated and host system for access by emulated system users
11/05/1996US5572702 Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
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