Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
09/1984
09/25/1984US4473881 Encachement apparatus
09/25/1984US4473878 Memory management unit
09/25/1984US4473877 Parasitic memory expansion for computers
09/25/1984CA1175156A1 Cache memory using a lowest priority replacement circuit
09/19/1984EP0119075A2 Faulty-memory processing method and apparatus
09/19/1984EP0118978A2 Address sequencer for pattern processing system
09/19/1984EP0118954A2 Volume recovery system for data sets in a word processing system
09/19/1984EP0118861A2 Volume recovery methodand apparatus
09/18/1984US4472790 Storage fetch protect override controls
09/18/1984US4472774 Encachement apparatus
09/18/1984CA1174767A1 Processor with means to address operands in microinstructions
09/12/1984EP0118053A2 Image signal processor
09/12/1984EP0117954A2 Bus networks for digital data processing systems and modules usable therewith
09/12/1984EP0117930A1 Interactive work station with auxiliary microprocessor for storage protection
09/11/1984US4471457 Supervisory control of peripheral subsystems
09/11/1984US4471432 Method and apparatus for initiating the execution of instructions using a central pipeline execution unit
09/11/1984US4471431 For use in a digital computer system
09/11/1984US4471430 In a digital computer system
09/11/1984US4471429 Apparatus for cache clearing
09/11/1984US4471349 Phantom raster generating apparatus scanning TV image memory in angular and orthogonal coordinates
09/11/1984CA1174374A1 Memory management unit for developing multiple physical addresses in parallel for use in a cache
09/11/1984CA1174373A1 Channel adapter for virtual storage system
09/05/1984EP0117837A2 User programmable bus configuration for microcomputers
09/05/1984EP0117836A2 Address-controlled automatic bus arbitration and address modification
09/05/1984EP0117735A1 Computer control system
09/05/1984EP0117493A2 Digital controller
09/05/1984EP0117408A2 Method and mechanism for load balancing in a multiunit system
09/05/1984EP0117344A2 Memory system
09/05/1984EP0117281A2 Updating data processing files
09/04/1984CA1173976A1 Information-signal recording apparatus employing record volume oriented identification signals
08/1984
08/29/1984EP0117220A2 Staging memory for massively parallel processor
08/29/1984EP0116883A2 Circuit arrangement for buffering command words
08/28/1984US4468730 Detection of sequential data stream for improvements in cache data storage
08/28/1984US4468729 In a data processing system
08/28/1984CA1173567A1 Shared virtual address translation unit for a multiprocessor system
08/28/1984CA1173565A1 Apparatus and method for selective cache clearing in a data processing system
08/22/1984EP0116455A2 Method and means for memory bank selection in a microprocessing system
08/22/1984EP0116366A2 Method for controlling storage of data sets in memory unit
08/22/1984EP0116344A2 Power backed-up dual memory system
08/22/1984EP0116081A1 Virtual memory addressing system and method
08/21/1984US4467443 Bit addressable variable length memory system
08/21/1984US4467421 Virtual storage system and method
08/21/1984US4467419 Data processing system with access to a buffer store during data block transfers
08/21/1984US4467414 Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
08/21/1984US4467411 Machine-implemented method of operating a storage subsystem
08/21/1984CA1173172A1 Data processing system having a uniquely organized memory using object-based information and a unique protection scheme for determining access rights to such information and using unique multilevel microcode techniques
08/21/1984CA1173171A1 Address expanding system
08/15/1984EP0115877A2 Critical system protection
08/15/1984EP0115609A2 Addressing device for the storage of several data processing units in a bus system
08/14/1984US4466059 Method and apparatus for limiting data occupancy in a cache
08/14/1984US4466056 Address translation and generation system for an information processing system
08/14/1984US4466017 Sync suppression scrambling of television signals for subscription TV
08/14/1984US4465901 For protecting a program of executable instructions during execution
08/14/1984CA1172771A1 Memory controller with interleaved queuing apparatus
08/08/1984EP0115344A2 Buffer control system
08/08/1984EP0115179A2 Virtual memory address translation mechanism with combined hash address table and inverted page table
08/08/1984EP0115036A2 A hierarchical memory system including separate cache memories for storing data and instructions
08/08/1984EP0114944A2 Method and apparatus for controlling a single physical cache memory to provide multiple virtual caches
08/08/1984EP0114852A1 Multi-dimensional-access memory system.
08/07/1984US4464717 For use in a microcomputer system
08/07/1984US4464713 Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a cache attached to the backing store
08/07/1984US4464712 For a data processing system
08/07/1984CA1172387A1 Selective use of restored file setups
08/07/1984CA1172378A1 Scheduling device operations in a buffered peripheral subsystem
08/07/1984CA1172375A1 Program call method
08/07/1984CA1172368A1 Method for automatic field width expansion in text processing system during interactive entry of displayed record selection criteria
08/01/1984EP0114522A2 ROM protection device
08/01/1984EP0114304A1 Vector processing hardware assist and method
08/01/1984EP0114221A2 Data base access process using a user-friendly menu
08/01/1984EP0114190A2 Data storage hierarchy
07/1984
07/31/1984US4463450 Semiconductor memory formed of memory modules with redundant memory areas
07/31/1984US4463424 Method for dynamically allocating LRU/MRU managed memory among concurrent sequential processes
07/31/1984US4463420 Multiprocessor cache replacement under task control
07/31/1984US4463270 MOS Comparator circuit
07/31/1984CA1171931A1 Channel interface circuit
07/31/1984CA1171700A1 Boring devices
07/24/1984CA1171548A1 Program identification encoding
07/24/1984CA1171542A1 Method for integrating structured data and string data on a text processing system
07/19/1984WO1984002799A1 A hierarchical memory system including separate cache memories for storing data and instructions
07/19/1984WO1984002784A1 Virtual memory address translation mechanism with controlled data persistence
07/18/1984EP0113612A2 Address conversion unit for multiprocessor system
07/18/1984EP0113476A2 Arrangement for converting a virtual address into a physical address for a paged working memory in a data processing system
07/18/1984EP0113460A2 Symbolic language data processing system
07/18/1984EP0113352A1 Database management system for controlling concurrent access to a database.
07/17/1984US4461003 Circuit arrangement for preventing a microcomputer from malfunctioning
07/17/1984US4461001 Deterministic permutation algorithm
07/17/1984US4460959 Logic control system including cache memory for CPU-memory transfers
07/17/1984US4460958 Window-scanned memory
07/17/1984CA1171183A1 Variable field partial write data merge mask system
07/11/1984EP0113240A2 Virtual memory address translation mechanism with controlled data persistence
07/10/1984US4459688 Access request selecting circuit
07/10/1984US4459662 Microcomputer having ROM mass memory for downloading main RAM memory with microcomputer instructions
07/10/1984US4459661 Channel address control system for a virtual machine system
07/10/1984CA1170779A1 Computer segmented memory management technique wherein two expandable memory portions are contained within a single segment
07/04/1984EP0112622A2 Error correction in buffer storage units
07/04/1984EP0112442A2 Data storage hierarchy and its use for data storage space management
07/04/1984EP0112367A1 Software protection methods and apparatus
07/03/1984US4458357 Circuit board identity generator
07/03/1984US4458349 Method for storing data words in fault tolerant memory to recover uncorrectable errors
07/03/1984US4458338 Circuit for checking memory cells of programmable MOS-integrated semiconductor memories
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