| Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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| 09/17/1997 | EP0795826A2 Systems and methods for implementing inter-device cell replacements |
| 09/17/1997 | EP0795820A2 Combination prefetch buffer and instructions cache |
| 09/17/1997 | EP0795159A1 Bus-to-bus bridge |
| 09/17/1997 | EP0728338B1 Compound document framework |
| 09/17/1997 | EP0708942B1 Method and structure for evaluating and enhancing the performance of cache memory systems |
| 09/17/1997 | EP0670062B1 Arrangement with plug-in functional units |
| 09/16/1997 | US5669014 System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width |
| 09/16/1997 | US5669003 In a data processing system |
| 09/16/1997 | US5668987 Database system with subquery optimizer |
| 09/16/1997 | US5668979 Storage of clipping plane data in successive bit planes of residual frame buffer memory |
| 09/16/1997 | US5668976 Error correction method and apparatus for disk drive emulator |
| 09/16/1997 | US5668975 Method of requesting data by interlacing critical and non-critical data words of multiple data requests and apparatus therefor |
| 09/16/1997 | US5668974 Memory with variable levels of interleaving and associated configurator circuit |
| 09/16/1997 | US5668973 Protection system for critical memory information |
| 09/16/1997 | US5668972 Method and system for efficient miss sequence cache line allocation utilizing an allocation control cell state to enable a selected match line |
| 09/16/1997 | US5668969 Address selective emulation routine pointer address mapping system |
| 09/16/1997 | US5668968 Two-level virtual/real set associative cache system and method with improved synonym detection |
| 09/16/1997 | US5668966 In a computer system |
| 09/16/1997 | US5668961 In a computer system |
| 09/16/1997 | US5668956 Bus system for use with information processing apparatus |
| 09/16/1997 | US5668949 System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource |
| 09/16/1997 | US5668945 Data security apparatus and method |
| 09/16/1997 | US5668815 Method for testing integrated memory using an integrated DMA controller |
| 09/16/1997 | US5668773 Synchronous burst extended data out DRAM |
| 09/16/1997 | CA2094657C Communication system links different independent databases and provides automatic updating of corresponding records in the databases |
| 09/12/1997 | WO1997033286A1 Method and apparatus useful in electronic encoders having a voltage level detection circuit |
| 09/12/1997 | WO1997033285A1 A modular cache memory battery backup system |
| 09/12/1997 | WO1997033229A1 A modular mirrored cache memory battery backup system |
| 09/12/1997 | WO1997033226A1 Programmable controller |
| 09/12/1997 | WO1997033225A1 Norris flash file system |
| 09/12/1997 | WO1997033217A1 Improved integrated circuit and method for using same |
| 09/12/1997 | CA2220391A1 A modular cache memory battery backup system |
| 09/12/1997 | CA2220340A1 A modular mirrored cache memory battery backup system |
| 09/11/1997 | DE19636087A1 Flash memory personal computer card |
| 09/11/1997 | DE19631386A1 Bus subscriber's plug-in arrangement |
| 09/10/1997 | EP0794646A2 Data management system and method for replicated data |
| 09/10/1997 | EP0794530A2 System for compression and buffering of a data stream |
| 09/10/1997 | EP0794496A1 Method and device for recording data, data recording medium, and method and device for reproducing data |
| 09/10/1997 | EP0794494A2 Self-checking and correcting of cache memory management |
| 09/10/1997 | EP0794484A2 Partitioned hard disk drives and partitioning scheme for hard disk drives |
| 09/10/1997 | EP0794479A1 Method and apparatus for providing dynamic network file system client authentication |
| 09/10/1997 | EP0793827A1 Method and structure for utilizing a dram array as second level cache memory |
| 09/10/1997 | EP0793824A1 User definable pictorial interface for accessing information in an electronic file system |
| 09/10/1997 | CN1159235A Method and device for recording data, data recording medium, and method and device for reproducing data |
| 09/09/1997 | US5666557 Method in a data processing system |
| 09/09/1997 | US5666545 Direct access video bus computer system and method for transferring video information using a dedicated video bus |
| 09/09/1997 | US5666540 Information processing system |
| 09/09/1997 | US5666532 Computer method and apparatus for asynchronous ordered operations |
| 09/09/1997 | US5666530 System for automatic synchronization of common file between portable computer and host computer via communication channel selected from a plurality of usable channels there between |
| 09/09/1997 | US5666527 System for dynamically changing logical data structure of database |
| 09/09/1997 | US5666516 Protected programmable memory cartridge having selective access circuitry |
| 09/09/1997 | US5666515 Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address |
| 09/09/1997 | US5666514 Cache memory containing extra status bits to indicate memory regions where logging of data should occur |
| 09/09/1997 | US5666513 Automatic reconfiguration of multiple-way cache system allowing uninterrupted continuing processor operation |
| 09/09/1997 | US5666510 Data processing device having an expandable address space |
| 09/09/1997 | US5666509 Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof |
| 09/09/1997 | US5666506 Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle |
| 09/09/1997 | US5666494 Queue management mechanism which allows entries to be processed in any order |
| 09/09/1997 | US5666482 Method and system for bypassing a faulty line of data or its associated tag of a set associative cache memory |
| 09/09/1997 | US5666480 Fault-tolerant hierarchical bus system and method of operating same |
| 09/09/1997 | US5666114 Method and means for managing linear mapped address spaces storing compressed data at the storage subsystem control unit or device level |
| 09/04/1997 | WO1997032252A1 Dynamically upgradeable disk array system and orthogonal signal multiplexing system therefor |
| 09/04/1997 | WO1997020264A3 Service order system having staged databases |
| 09/04/1997 | CA2247092A1 Orthogonal signal multiplexing system |
| 09/03/1997 | EP0793183A1 Programmable options for volume mount on a computing system |
| 09/03/1997 | EP0793180A2 High speed flexible slave interface for parallel common bus to local cache buffer |
| 09/03/1997 | EP0793179A2 System and method for emulating a segmented virtual address space by a microprocessor that provides a non-segmented virtual address space |
| 09/03/1997 | EP0793178A2 Writeback buffer and copyback procedure in a multi-processor system |
| 09/03/1997 | EP0793175A1 Computer system having resume function |
| 09/03/1997 | EP0793174A2 Error detection and correction method and apparatus for computer memory |
| 09/03/1997 | EP0793173A2 Non-volatile semicon-ductor storage unit having a correction coding circuit |
| 09/03/1997 | EP0793169A1 Identification interface |
| 09/03/1997 | EP0792497A1 Active security device with electronic memory |
| 09/03/1997 | EP0760975A4 Guarded memory system and method |
| 09/03/1997 | EP0616709B1 Semaphore bypass |
| 09/03/1997 | CN1158668A Method and system for storing data blocks in a memory device |
| 09/03/1997 | CN1158523A Method of activating and executing the protected function in a communication system |
| 09/03/1997 | CN1158461A Data acquiring apparatus |
| 09/03/1997 | CN1158456A Information service processor |
| 09/03/1997 | CN1158453A High effective electronic data protection method |
| 09/03/1997 | CN1158452A Method for programming data processing system internal storage modulus |
| 09/02/1997 | US5664230 Data processing with adaptable external burst memory access |
| 09/02/1997 | US5664225 Circuit for disabling an address masking control signal when a microprocessor is in a system management mode |
| 09/02/1997 | US5664221 System for reconfiguring addresses of SCSI devices via a device address bus independent of the SCSI bus |
| 09/02/1997 | US5664217 Method of avoiding physical I/O via caching with prioritized LRU management |
| 09/02/1997 | US5664209 Document processing apparatus for processing information having different data formats |
| 09/02/1997 | US5664187 Method and system for selecting data for migration in a hierarchic data storage system using frequency distribution tables |
| 09/02/1997 | US5664186 Computer file management and backup system |
| 09/02/1997 | US5664178 Method and system for organizing internal structure of a file |
| 09/02/1997 | US5664177 Data processing system having a data structure with a single, simple primitive |
| 09/02/1997 | US5664176 Computer storage device |
| 09/02/1997 | US5664174 System and method for discovering similar time sequences in databases |
| 09/02/1997 | US5664161 Address-translatable graphic processor, data processor and drawing method with employment of the same |
| 09/02/1997 | US5664160 Computer program product for simulating a contiguous addressable data space |
| 09/02/1997 | US5664159 Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register |
| 09/02/1997 | US5664154 M/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the addressed location's dirty bit indicates a write-back |
| 09/02/1997 | US5664153 Page open/close scheme based on high order address bit and likelihood of page access |
| 09/02/1997 | US5664151 System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions |
| 09/02/1997 | US5664150 Computer system with a device for selectively blocking writebacks of data from a writeback cache to memory |
| 09/02/1997 | US5664149 Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol |