Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
07/2004
07/20/2004US6765445 Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
07/20/2004US6765444 Cross clocked lock detector circuit for phase locked loop
07/20/2004US6765435 Phase locked loop demodulator and demodulation method using feed-forward tracking error compensation
07/20/2004US6765424 Stratum clock state machine multiplexer switching
07/20/2004US6765423 Semiconductor circuit having clock synchronous receiver circuit
07/20/2004US6765421 Duty-cycle correction circuit
07/20/2004US6765419 Dynamic delay line control
07/20/2004US6764891 Physically defined varactor in a CMOS process
07/20/2004CA2358790C Out-of-sync detector, receiver and optical receiver
07/15/2004WO2004059902A2 Method and device for extracting a clock pulse frequency underlying a data flow
07/15/2004WO2004059847A1 Digitally controllable oscillator
07/15/2004WO2004059846A1 Analogue/digital delay locked loop
07/15/2004WO2004059844A2 Pahse locked loop comprising a variable delay and a discrete delay
07/15/2004WO2004042924A3 Vco gain tracking for modulation gain setting calibration
07/15/2004WO2004025842A3 System for efficient recovery of node-b buffered data following mac layer reset
07/15/2004WO2003088100A3 Automatic phase lock loop design using geometric programming
07/15/2004US20040139230 SIP service method in a network having a NAT
07/15/2004US20040136483 Clock recovery method by phase selection
07/15/2004US20040136440 Spread spectrum clock generation circuit, jitter generation circuit and semiconductor device
07/15/2004US20040135642 Synchronizing circuit provided with hysteresis phase comparator
07/15/2004US20040135641 System and method to reduce glitch disturbance for phase/frequency detecting device
07/15/2004US20040135640 Phase-locked loop with conditioned charge pump output
07/15/2004US20040135639 Fast locking phase-locked loop
07/15/2004US20040135605 Delay locked loops having delay time compensation and methods for compensating for delay time of the delay locked loops
07/15/2004US20040135604 Delay locked loops having blocking circuits therein that enhance phase jitter immunity and methods of operating same
07/15/2004US20040135603 Differential charge pump and method therefor, and phase locked loop and method therefor using the pump and method
07/15/2004US20040135601 Clock multiplier circuit
07/15/2004DE10258406A1 Detecting phase position of signal relative to digital signal involves oversampling digital signal with sampling signal derived from signal to derive two sampling value groups per data signal data bit
07/15/2004DE10257680A1 Schaltungsanordnung zur Leckstrombegrenzung, Abtast-Halte-Schaltung mit der Schaltungsanordnung sowie Ladungspumpenschaltung mit der Schaltungsanordnung Circuit arrangement for limiting leakage current, sample and hold circuit with the circuit arrangement as well as the charge pump circuit with the circuit arrangement
07/15/2004DE10257181B3 Phasenregelkreis mit Modulator Phase-locked loop with a modulator
07/15/2004DE10047379B4 Bauelement mit akustisch aktivem Material Component with acoustically active material
07/14/2004EP1436996A1 Interactive protocol for remote management of access control to scrambled data
07/14/2004EP1436958A1 A digital implementation of multi-channel demodulators
07/14/2004EP1436897A1 Dual loop phase lock loops using dual control voltage supply regulators
07/14/2004EP1436896A1 Phase-switched dual-mode divider counter circuit for a frequency synthesizer
07/14/2004EP1436826A2 A high performance integrated circuit regulator with substrate transient suppression
07/14/2004EP1410510A4 Pll cycle slip compensation
07/14/2004EP1362413B1 Compensation method and compensating device for a pll circuit for two-point modulation
07/14/2004EP1323232B1 Element made of acoustic active material
07/14/2004CN1512659A Oscillator using guide circuit to increase responding speed
07/14/2004CN1157905C AFC circuit and carrier reproducing circuit
07/14/2004CN1157904C Timing recovery system for digital signal processor
07/13/2004US6763474 System for synchronizing nodes in a heterogeneous computer system by using multistage frequency synthesizer to dynamically adjust clock frequency of the nodes
07/13/2004US6763080 Synchronous signal processing system
07/13/2004US6763079 Semiconductor device allowing easy confirmation of operation of built in clock generation circuit
07/13/2004US6762649 System and method for automatic parameter adjustment within a phase locked loop system
07/13/2004US6762648 Device and method for production of a clock signal
07/13/2004US6762635 Clock generator, particularly for USB devices
07/13/2004US6762634 Dual-loop PLL with DAC offset for frequency shift while maintaining input tracking
07/13/2004US6762633 Delay locked loop circuit with improved jitter performance
07/13/2004US6762631 Lock detection circuit for a phase locked loop circuit
07/13/2004US6762629 VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors
07/08/2004WO2004038918A3 Method and device for generating a clock signal with predetermined clock signal properties
07/08/2004US20040132421 Mobile communications device with GPS receiver and common clock source
07/08/2004US20040131136 Timesliced discrete-time phase locked loop
07/08/2004US20040131105 Frequency converter and radio communications system employing the same
07/08/2004US20040131058 Multiple high-speed bit stream interface circuit
07/08/2004US20040130962 Delayed locked loop implementation in a synchronous dynamic random access memory
07/08/2004US20040130373 Low-swing impedance controlled unity gain differential clock driver
07/08/2004US20040130372 Semiconductor apparatus
07/08/2004US20040130371 Unity gain interpolator for delay locked loops
07/08/2004US20040130366 Method and system for delay control in synchronization circuits
07/08/2004US20040130365 High resolution interleaved delay chain
07/08/2004US20040130364 Charge pump circuit and PLL circuit using same
07/08/2004US20040130358 Frequency output generation
07/08/2004DE19946699B4 Vorrichtung zur Bestimmung der Drehzahl von Gleichstrommotoren An apparatus for determining the speed of DC motors
07/08/2004DE10257476A1 Injection-Locked-Oscillator-Schaltkreis und Recheneinheit Injection-locked oscillator circuit and computing unit
07/08/2004DE10227839B4 Phasendifferenzerfassungsschaltung Phase difference detecting circuit
07/07/2004EP1435694A2 Spread spectrum clock generation circuit jitter generation circuit and semiconductor device
07/07/2004CN1511400A Method and apparatus for desynchronizing DS-3 signal and/or E3 signal from data portion of STS/STM payload
07/07/2004CN1511377A High-speed programmable synchronous counter for use in phase locked loop
07/07/2004CN1511278A Efficient current-feedback power supply and applications thereof
07/07/2004CN1511261A Low-loss tunable ferro-electric device and method of characterization
07/07/2004CN1510839A Spread spectrum clock generating circuit, vibrating producing circuit and semiconductor device
07/07/2004CN1510838A Correcting system and method for gain error generated by jump density variation
07/07/2004CN1510829A Phase-locked ring demodulator with feed forward tracking error compensation and demodulation method thereof
07/07/2004CN1510577A Data transferring system for high speed transference
07/07/2004CN1510432A Radio frequency pulse angle phase setting method and circuit thereof
07/07/2004CN1156993C Moving station capable of controlling frequency automaticall
07/07/2004CN1156992C Method for reducing interfere from adjacent channels for wireless transmitting device and apparatus concerned starting
07/07/2004CN1156981C Phase compensation circuit for data phase-locked loop
07/07/2004CN1156975C Clock generation circuit, Serial/parallel converter and parallel/serial converter
07/07/2004CN1156958C Oscillator with voltage control
07/06/2004US6760575 Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications
07/06/2004US6760398 Switched phase dual-modulus prescaler circuit having means for reducing power consumption
07/06/2004US6760395 Device for timing reconstruction of a data channel transported on a packet network and its process
07/06/2004US6760394 CMOS lock detect with double protection
07/06/2004US6760389 Data recovery for non-uniformly spaced edges
07/06/2004US6759912 Phase locked loop
07/06/2004US6759911 Delay-locked loop circuit and method using a ring oscillator and counter-based delay
07/06/2004US6759910 Phase locked loop (PLL) frequency synthesizer and method
07/06/2004US6759909 RF energy dispersal in systems consisting of aggregated computing elements as subsystems
07/06/2004US6759904 Large gain range, high linearity, low noise MOS VGA
07/06/2004US6759883 Variable delay circuit and method, and delay locked loop, memory device and computer system using same
07/06/2004US6759882 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal
07/06/2004US6759881 System with phase jumping locked loop circuit
07/06/2004US6759875 Voltage controlled oscillation circuit
07/06/2004US6759838 Phase-locked loop with dual-mode phase/frequency detection
07/01/2004WO2004055989A2 Low lock time delay locked loops using time cycle supppressor
07/01/2004WO2004055988A2 Coarse delay tuner circuits with edge suppressors in delay locked loops