Patents
Patents for G06F 9 - Arrangements for programme control, e.g. control unit (241,428)
06/1988
06/01/1988EP0268865A2 Method and apparatus to provide faster update time during an improved subsystem checkpoint cycle
05/1988
05/31/1988US4748587 Device for improving detection of unoperational states in non-attended driven processor
05/31/1988US4748586 Data processing system with interrupt facilities
05/31/1988US4748585 Method of operating an electronic computer processor
05/31/1988US4748558 Load balancing control method for a loosely coupled multi-processor system and a device for realizing same
05/31/1988US4748439 Memory apparatus and method for retrieving sequences of symbols including variable elements
05/31/1988CA1237525A1 Queue administration method and apparatus
05/25/1988EP0268435A2 Multinode reconfigurable pipeline computer
05/25/1988EP0268293A2 Display method in software development support system
05/25/1988EP0268285A2 Method and circuit arrangement for the initial loading of a secondary computer
05/25/1988EP0268264A2 Control system for vector processor
05/25/1988EP0268182A2 Fuzzy computers
05/25/1988EP0268069A2 Method of forming a message file in a computer
05/25/1988EP0268052A1 Method for task switching on receipt of an interrupt request in a processor system
05/24/1988US4747130 Resource allocation in distributed control systems
05/24/1988US4747127 Telecommunication switching system
05/24/1988US4747066 Arithmetic unit
05/24/1988US4747046 Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch
05/24/1988US4747045 Information processing apparatus having an instruction prefetch circuit
05/24/1988US4747044 Direct execution of software on microprogrammable hardware
05/24/1988US4747040 Dual operating system computer
05/19/1988WO1988003682A1 I/o system for off-loading operating system functions
05/19/1988WO1988003681A1 Pipeline control system
05/18/1988EP0267796A2 Method for improved code generation in reduced instruction set computers
05/18/1988EP0267628A2 Microprocessor with a cache memory
05/18/1988EP0267613A2 Micro processor capable of being connected with coprocessor
05/18/1988EP0267612A2 Timer/counter using a register block
05/18/1988EP0267379A2 Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design
05/18/1988EP0157819B1 Multi-processing stored program controlled telecommunication establishment
05/18/1988EP0157075B1 Modular data processing system
05/17/1988US4745605 Control word error detection and classification
05/17/1988US4745572 Software editing instrument
05/17/1988US4745547 In a data processing system
05/17/1988US4745130 Tyrosine, calcium chloride, ephedrine, dopamine
05/17/1988CA1236923A1 Architecture for a distributive microprocessing system
05/11/1988EP0266799A2 Single chip microcomputer having multi-timer function
05/11/1988EP0266505A2 Versioning of message formats in a 24-hour operating environment
05/10/1988US4744048 Display context switching arrangement
05/10/1988US4744043 Data processor execution unit which receives data with reduced instruction overhead
05/10/1988US4744028 Methods and apparatus for efficient resource allocation
05/10/1988EP0168406A4 Floating point condition code generation.
05/10/1988CA1236584A1 Parallel processing system
05/10/1988CA1236583A1 Device for improving detection of unoperational states in non-attended driven processor
05/04/1988EP0266300A2 N-dimensional modular multiprocessor lattice architecture
05/04/1988EP0266145A2 Electronic data processing apparatus for improved algebraic expression manipulation
05/04/1988EP0266144A2 A calculator having a user-accessible object stack for the uniform application of mathematical functions and logical operations to a multiplicity of object types
05/04/1988EP0266016A2 Automatic circuit board configuration
05/04/1988EP0265972A2 Control of the program counter used in a pipelined computer
05/04/1988EP0265949A2 Debugging microprocessor
05/04/1988EP0265948A2 Data processor capable of immediately calculating branch address in relative address branch
05/04/1988CN85102313B Instruetion processor
05/03/1988US4742467 Automated programming system for machine creation of applications program source code from non-procedural terminal input
05/03/1988US4742454 Apparatus for buffer control bypass
05/03/1988US4742453 Pipeline-controlled information processing system for generating updated condition code
05/03/1988US4742452 Computer system including address driven program interrupt system
05/03/1988US4742451 Instruction prefetch system for conditional branch instruction for central processor unit
05/03/1988US4742450 Method for facilitating the interchange of data stored in a Unix file
05/03/1988US4742449 Microsequencer for a data processing system using a unique trap handling technique
05/03/1988CA1235958A1 Method of forming images
04/1988
04/27/1988EP0265134A1 Method and apparatus for configuring a measurement instrument and configurable instrument itself
04/27/1988EP0265108A2 Cache storage priority
04/27/1988EP0264568A2 Serialisation of system events in a multiprocessing system
04/26/1988US4740915 Method of controlling a microprocessor to monitor input signals at irregular mutually intersecting intervals
04/26/1988US4740910 Multiprocessor system
04/26/1988US4740893 Method for reducing the time for switching between programs
04/26/1988US4740892 For executing a processing of instructions
04/26/1988CA1235816A1 Error recovery system in a data processor having a control storage
04/26/1988CA1235784A1 Arrangement for the generation of information and/or an instruction intended for input to the program memory of a computer
04/21/1988DE3634209A1 Computer system
04/20/1988EP0264325A1 Automatic device for making a processor compatible with the bus of another processor
04/20/1988EP0264317A1 Apparatus for the optimization of the performances of real-time primitives of a real-time executive kernel on multiprocessor architectures
04/20/1988EP0264235A2 Apparatus and method for improving cache access throughput in pipelined processors
04/20/1988EP0264216A2 Implied domain addressing
04/20/1988EP0264215A2 Fast entry to emulation
04/20/1988EP0264048A2 Thirty-two bit bit-slice
04/20/1988CN87106765A Process and equipment executing two instruction sequence on predetermined order
04/19/1988US4739475 Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability
04/19/1988US4739472 Information processing device capable of rapidly processing instructions of different groups
04/19/1988US4739471 Method and means for moving bytes in a reduced instruction set computer
04/19/1988US4739470 Data processing system
04/19/1988CA1235525A1 Field-directed screen help technique
04/19/1988CA1235521A1 Log on and log off instruction system
04/13/1988EP0263447A2 A method and apparatus for implementing a branch and return on address instruction in a digital data processing system
04/13/1988EP0263288A2 Extended floating point operations supporting emulation of source instruction execution
04/13/1988EP0263286A2 Data processing system for emulating the execution of instructions
04/13/1988EP0126125B1 Multiple control stores for a pipelined microcontroller
04/13/1988EP0126124B1 Multiple control stores in a pipelined microcontroller for handling nested subroutines
04/13/1988EP0124597B1 Multiple control stores in a pipelined microcontroller for handling jump and return subroutines
04/13/1988CN87106625A Process and equipment executing two instruction sequence on predetermined order
04/12/1988US4737933 CMOS multiport general purpose register
04/12/1988US4737932 Processor
04/12/1988US4737908 Buffer memory control system
04/12/1988CA1235230A1 Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
04/12/1988CA1235227A1 High speed program store with bootstrap
04/07/1988WO1988002514A1 Method and device to execute two instruction sequences in an order determined in advance
04/07/1988WO1988002513A1 Method and device to execute two instruction sequences in an order determined in advance
04/07/1988DE3632139A1 Method of executing two programs which are written in different programming languages
04/06/1988EP0262759A1 User interface simulation and management for program-controlled apparatus
04/06/1988EP0262750A2 Very large scale parallel computer
04/06/1988EP0262636A2 Circuit arrangement for selecting and/or aligning data units in data processors