Patents
Patents for G06F 9 - Arrangements for programme control, e.g. control unit (241,428)
11/1988
11/08/1988US4783783 Data processing system having pipeline arithmetic/logic units
11/08/1988US4783747 Control device for an automatic vending machine
11/08/1988US4783738 Adaptive instruction processing by array processor having processor identification and data dependent status registers in each processing element
11/08/1988US4783736 Digital computer with multisection cache
11/08/1988US4783734 Computer system with variable length process to process communication
11/08/1988US4783731 Multicomputer system having dual common memories
11/08/1988CA1244555A1 Process transparent multi storage mode data transfer and buffer control
11/08/1988CA1244554A1 Pageable branch history table
11/03/1988WO1988008584A1 Method and apparatus for implementing multiple lock indicators in a multiprocessor computer system
11/03/1988WO1988008579A1 Apparatus and method for a node to obtain access to a bus
11/03/1988WO1988008572A1 Commander node method and apparatus for assuring adequate access to system ressources in a multiprocessor computer system
11/03/1988WO1988008571A1 Method and apparatus for initiating transactions on a multiprocessor computer system employing multiple lock indications
11/03/1988WO1988008570A1 Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system
11/03/1988WO1988008569A1 Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
11/03/1988WO1988008568A1 Parallel-processing system employing a horizontal architecture comprising multiple processing elements and interconnect circuit with delay memory elements to provide data paths between the processing elements
11/03/1988WO1988008564A1 A method of communicating data between the cpu of a host computer system and the cpu of a co-processor computer system
11/03/1988DE3804956A1 Addressing unit
11/02/1988EP0289288A2 Portable computer
11/02/1988EP0289072A2 Verfahren zum Betrieb eines Multiprozessorsystems mit Synchronisierungsmitteln zur Feststellung einer globalen binären Aussage und ein Multiprozessor mit Synchronisation zum bestimmen derselben, insbesondere zur Kompaktierung.
11/02/1988EP0288760A2 Data processor capable of correctly re-executing instructions
11/02/1988EP0288606A2 Computer system employing a CPU having two mutually incompatible addressing modes
11/02/1988EP0047238B1 Data processing system
11/01/1988US4782506 Arrangement for operating and maintaining a telecommunications system
11/01/1988US4782463 Method for generating display screens for a set of application programs by calling screen management subroutines
11/01/1988US4782444 Compilation using two-colored pebbling register allocation method such that spill code amount is invariant with basic block's textual ordering
11/01/1988US4782442 Time-sharing computer system operable in a host TSS mode and a terminal TSS mode
11/01/1988US4782441 Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions
11/01/1988CA1244142A1 Distributed data management mechanism
10/1988
10/27/1988DE3812607A1 Verfahren und schaltungsanordnung zur bestimmung der resourcenkonfiguration von in einem schlitz eines computers aufgenommenen schaltungen Circuits recorded method and circuit arrangement for the determination of the resource configuration of a slot of a computer
10/27/1988DE3711651A1 Data processing system with a standard sequential circuit and at least one special sequential circuit
10/26/1988EP0288146A2 Garbage collection in a virtual memory system
10/26/1988EP0287600A1 Method and device to execute two instruction sequences in an order determined in advance.
10/26/1988CN87201720U Multiplex semiconductor time relay
10/25/1988US4780843 Wait mode power reduction system and method for data processor
10/25/1988US4780825 Text compiling device
10/25/1988US4780822 Semaphore circuit for shared memory cells
10/25/1988US4780821 Method for multiple programs management within a network having a server computer and a plurality of remote computers
10/25/1988US4780820 Control flow computer using mode and node driving registers for dynamically switching between parallel processing and emulation of von neuman processors
10/25/1988US4780819 Emulator system utilizing a program counter and a latch coupled to an emulator memory for reducing fletch line of instructions stored in the emulator memory
10/25/1988US4780811 Vector processing apparatus providing vector and scalar processor synchronization
10/25/1988US4780807 Pipeline processor with overlapped fetch and execute cycles
10/20/1988WO1988008162A1 Data transfer system for a multiprocessor computing system
10/20/1988WO1988008161A1 An operations controller for a fault tolerant multiple node processing system
10/20/1988WO1988007242A3 Arithmetic computation modifier based upon data dependent operations
10/19/1988EP0287301A2 Input/output system for multiprocessors
10/19/1988EP0287295A2 Multiple I/O bus virtual broadcast of programmed I/O instructions
10/19/1988EP0287115A2 Coprocessor and method of controlling the same
10/19/1988EP0286807A2 Method for regulating access by concurrent transactions to resources
10/19/1988CN88200348U Multiple external controller in common for microcomputer groups
10/19/1988CN88100756A Mode conversion of computer commands
10/18/1988US4779195 Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor
10/18/1988US4779194 Event allocation mechanism for a large data processing system
10/18/1988US4779192 Vector processor with a synchronously controlled operand fetch circuits
10/18/1988US4779188 Selective guest system purge control
10/18/1988US4779187 Method and operating system for executing programs in a multi-mode microprocessor
10/18/1988CA1243411A1 Control means in a digital computer
10/12/1988EP0286361A2 Method of verifying computer software
10/12/1988EP0286356A2 Stack with unary encoded stack pointer
10/12/1988EP0286354A2 A method and apparatus for modifying micro-instructions using a macro-instruction pipeline
10/12/1988EP0286352A2 Entry point mapping and skipping method and apparatus
10/12/1988EP0286260A2 Group-relative addressing system
10/12/1988EP0285892A2 Clock skew compensation system for pipeline processors
10/12/1988EP0285634A1 Method to execute two instruction sequences in an order determined in advance.
10/12/1988EP0061462B1 Multi-system portable paging device
10/11/1988US4777594 Data processing apparatus and method employing instruction flow prediction
10/11/1988US4777592 Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
10/11/1988US4777590 Portable computer
10/11/1988US4777588 General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance
10/11/1988US4777587 System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
10/11/1988US4777585 Analogical inference method and apparatus for a control system
10/11/1988US4777355 IC card and system for checking the functionality thereof
10/11/1988CA1243124A1 Look-ahead instruction fetch control for a cache memory
10/06/1988WO1988007724A1 Control of multiple processors executing in parallel regions
10/06/1988WO1988007720A1 Dynamically assignable shared register sets
10/06/1988WO1988007719A2 Apparatus for iconographically representing and executing a program
10/06/1988WO1988007718A1 Arrangement for software emulation
10/05/1988EP0285346A2 Cache memory device
10/05/1988EP0285310A2 Device for saving and restoring register information
10/05/1988EP0285192A1 Pipeline system with parallel data identification
10/05/1988EP0285003A2 Apparatus and method controlled to function in a series of states of operation for effecting data transfer in a communication system
10/05/1988EP0284924A2 Data processing network with updating of files
10/05/1988EP0284764A2 Improved user transaction guidance
10/04/1988US4775934 Method for concurrent logic program
10/04/1988US4775933 Address generation system
10/04/1988US4775931 Dynamically configured computing device
10/04/1988US4775927 Processor including fetch operation for branch instruction with control tag
10/04/1988CA1242805A1 Rule acquisition for expert systems
10/04/1988CA1242802A1 Microprocessor with improved instruction cycle
10/04/1988CA1242801A1 Control unit for a microprogrammed processor
09/1988
09/28/1988EP0284364A2 High speed computer system
09/28/1988EP0284327A2 Shared micro-ram with micro-rom linking
09/28/1988EP0284100A2 Information processor having instruction prefetch function
09/28/1988EP0284060A2 Chip test condition selection apparatus
09/28/1988EP0283581A2 Computer system with mode conversion of computer commands
09/27/1988US4774688 Data processing system for determining min/max in a single operation cycle as a result of a single instruction
09/22/1988WO1988007242A2 Arithmetic computation modifier based upon data dependent operations
09/22/1988WO1988007239A1 Apparatus and method for synchronization of arithmetic exceptions in parallel pipelined execution units
09/22/1988WO1988007238A1 High-speed floating point operation system
09/22/1988WO1988007237A1 High-speed floating point arithmetic unit
09/22/1988WO1988007236A1 High-speed floating point arithmetic unit