| Patents for G06F 9 - Arrangements for programme control, e.g. control unit (241,428) |
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| 08/05/1997 | US5655146 Coexecution processor isolation using an isolation process or having authority controls for accessing system main storage |
| 08/05/1997 | US5655141 Method and system for storing information in a processing system |
| 08/05/1997 | US5655139 Execution unit architecture to support X86 instruction set and X86 segmented addressing |
| 08/05/1997 | US5655135 System for write protecting a bit that is hardware modified during a read-modify-write cycle |
| 08/05/1997 | US5655134 Network structure storing and retrieval method for a data processor |
| 08/05/1997 | US5655133 Massively multiplexed superscalar Harvard architecture computer |
| 08/05/1997 | US5655132 Register file with multi-tasking support |
| 08/05/1997 | US5655131 SIMD architecture for connection to host processor's bus |
| 08/05/1997 | US5655125 Register for identifying processor characteristics |
| 08/05/1997 | US5655124 Selective power-down for high performance CPU/system |
| 08/05/1997 | US5655122 Optimizing compiler with static prediction of branch probability, branch frequency and function frequency |
| 08/05/1997 | US5655120 Method for load balancing in a multi-processor system where arising jobs are processed by a plurality of processors under real-time conditions |
| 08/05/1997 | US5655115 Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation |
| 08/05/1997 | US5655114 System and device for prefetching command and parameters to be processed with least frequent bus access |
| 08/05/1997 | US5655112 Method and apparatus for enabling data paths on a remote bus |
| 08/05/1997 | US5655111 In-circuit emulator |
| 08/05/1997 | US5655101 Accessing remote data objects in a distributed memory environment using parallel address locations at each local memory to reference a same data object |
| 08/05/1997 | US5655099 Electronic device with microprocessor and banked memory and method of operation |
| 08/05/1997 | US5655098 High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format |
| 08/05/1997 | US5655097 High performance superscalar microprocessor including an instruction cache circuit for byte-aligning CISC instructions stored in a variable byte-length format |
| 08/05/1997 | US5655096 Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution |
| 08/05/1997 | US5655081 System for monitoring and managing computer resources and applications across a distributed computing environment using an intelligent autonomous agent architecture |
| 08/05/1997 | US5655080 Distributed hash group-by cooperative processing |
| 08/05/1997 | US5655074 Method of analyzing software |
| 08/05/1997 | US5655067 Animation generating method in a design supporting system |
| 08/05/1997 | US5654950 Method for protecting data recorded on a partial read-only memory (ROM) medium from unauthorized copying |
| 07/31/1997 | WO1997027557A1 Process management system and method |
| 07/31/1997 | WO1997027548A1 Dance/multitude concurrent computation |
| 07/31/1997 | WO1997027544A1 Processor with accelerated array access bounds checking |
| 07/31/1997 | WO1997027540A1 Graphic operating surface for programming programmable controllers |
| 07/31/1997 | WO1997027539A1 Methods and apparatuses for stack caching |
| 07/31/1997 | WO1997027538A1 Hierarchical scan logic for out-of-order load/store execution control |
| 07/31/1997 | WO1997027537A2 A processor for executing instruction sets received from a network or from a local memory |
| 07/31/1997 | WO1997027536A1 Instruction folding for a stack-based machine |
| 07/31/1997 | WO1997012339A3 Computing system for processing information flows |
| 07/31/1997 | DE19702326A1 Self-timed algorithmic device |
| 07/31/1997 | CA2243830A1 Process management system and method |
| 07/31/1997 | CA2243642A1 Dance/multitude concurrent computation |
| 07/30/1997 | EP0786730A1 High performance, low cost microprocessor |
| 07/30/1997 | EP0786724A1 Method and apparatus for transferring information between computing environments |
| 07/30/1997 | EP0786723A2 Document management systems using object- and agent-oriented methods |
| 07/30/1997 | EP0786722A1 A method and system for improving emulation performance |
| 07/30/1997 | EP0786109A2 Object-oriented system for configuration history management |
| 07/30/1997 | EP0769170A4 Computer virus trap |
| 07/30/1997 | EP0749598A4 Integrated control system for industrial automation applications |
| 07/30/1997 | EP0696368B1 Method and apparatus for enterprise desktop management |
| 07/30/1997 | EP0571395B1 System for distributed multiprocessor communication |
| 07/30/1997 | CN1155698A Method for real time computer controlled by a real time operation system |
| 07/30/1997 | CN1155694A Method and apparatus for subclassing system object model classes in dynamic languages |
| 07/29/1997 | US5652916 Prestaging method, buffer management method and file system |
| 07/29/1997 | US5652911 Multinode distributed data processing system for use in a surface vehicle |
| 07/29/1997 | US5652910 Devices and systems with conditional instructions |
| 07/29/1997 | US5652909 Computer implemented method for improved debugging of a data flow program |
| 07/29/1997 | US5652907 High speed mask and logical combination operations for parallel processor units |
| 07/29/1997 | US5652906 Data driven processor with improved initialization functions because operation data shares address space with initialization data |
| 07/29/1997 | US5652904 Non-reconfigurable microprocessor-emulated FPGA |
| 07/29/1997 | US5652903 DSP co-processor for use on an integrated circuit that performs multiple communication tasks |
| 07/29/1997 | US5652900 Data processor having 2n bits width data bus for context switching function |
| 07/29/1997 | US5652890 Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode |
| 07/29/1997 | US5652889 Alternate execution and interpretation of computer program having code at unknown locations due to transfer instructions having computed destination addresses |
| 07/29/1997 | US5652888 System for interconnecting software components in an object oriented programming environment using a separate editor object for each run-time object instantiated for each selected component |
| 07/29/1997 | US5652887 Dynamic Meta commands for peripheral devices |
| 07/29/1997 | US5652886 System for loading a boot program into an initially blank programmable memory of a microprocessor using state machine and serial bus |
| 07/29/1997 | US5652885 Interprocess communications system and method utilizing shared memory for message transfer and datagram sockets for message control |
| 07/29/1997 | US5652884 Method and apparatus for dynamic update of an existing object in an object editor |
| 07/29/1997 | US5652879 Dynamic value mechanism for computer storage container manager enabling access of objects by multiple application programs |
| 07/29/1997 | US5652875 Implementation of a selected instruction set CPU in programmable hardware |
| 07/29/1997 | US5652869 System for executing and debugging multiple codes in a multi-architecture environment using jacketing means for jacketing the cross-domain calls |
| 07/29/1997 | US5652858 Method for prefetching pointer-type data structure and information processing apparatus therefor |
| 07/29/1997 | US5652853 Multi-zone relocation facility computer memory system |
| 07/29/1997 | US5652852 Processor for discriminating between compressed and non-compressed program code, with prefetching, decoding and execution of compressed code in parallel with the decoding, with modified target branch addresses accommodated at run time |
| 07/29/1997 | US5652850 In a computer |
| 07/29/1997 | US5652829 Feature merit generator |
| 07/29/1997 | US5652823 Video data encoder and decoder |
| 07/29/1997 | US5652774 Method and apparatus for decreasing the cycle times of a data processing system |
| 07/29/1997 | US5652584 Data format converter |
| 07/29/1997 | US5651676 Method of organizing and storing simulated scenery in a flight simulation system |
| 07/24/1997 | WO1997026611A1 Deferred billing, broadcast, electronic document distribution system and method |
| 07/24/1997 | WO1997026597A1 An object oriented programming based global registry system, method, and article of manufacture |
| 07/24/1997 | WO1997026596A1 Distributed processing |
| 07/24/1997 | WO1997026595A1 Distributed processing |
| 07/24/1997 | WO1997026594A1 Processor system |
| 07/24/1997 | WO1997026587A1 Automation device |
| 07/23/1997 | EP0785630A2 Time multiplexing in field programmable gate arrays |
| 07/23/1997 | EP0785507A1 Data transfer system |
| 07/23/1997 | EP0785506A1 Optimizing compiler using interprocedural dataflow analysis |
| 07/23/1997 | EP0785505A2 Method of securing the collaboration between objects of an object oriented program |
| 07/23/1997 | EP0785504A2 Out of order execution of load instructions in a superscalar processor |
| 07/23/1997 | EP0785500A1 Storage device and method for data sharing |
| 07/23/1997 | EP0784893A1 Hierarchical communication system providing intelligent data, program and processing migration |
| 07/23/1997 | EP0784836A1 Data communication system |
| 07/23/1997 | EP0784818A1 Microprocessor programming using a state machine |
| 07/23/1997 | EP0784817A2 A method and system for updating software within a telecommunications switch without interrupting existing communication |
| 07/23/1997 | EP0664027B1 Program modeling system |
| 07/23/1997 | EP0528024B1 Improved error reporting for translated code execution |
| 07/23/1997 | CN1155340A Computer system having client-server architecture |
| 07/23/1997 | CN1155118A Program-controlled execution and display method |
| 07/22/1997 | US5651127 Integrated circuit |
| 07/22/1997 | US5651125 High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations |
| 07/22/1997 | US5651124 Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state |