| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 08/07/2013 | CN103236836A LUT (look-up table) structure with MUX (multiplexer) mode and EDA (electronic design automation) optimization method matching with LUT structure |
| 08/07/2013 | CN103236835A Signal isolation grid circuit |
| 08/07/2013 | CN103236834A Circuit, for limiting high-side floating power supply low level undershoot, in floating gate drive chip |
| 08/07/2013 | CN103236833A Photoelectric feedback chaotic laser reservoir parallel calculating device |
| 08/07/2013 | CN102522978B Isolation type power transistor driver |
| 08/07/2013 | CN102204105B An i/o circuit and integrated circuit |
| 08/07/2013 | CN102035516B Input/output circuit |
| 08/07/2013 | CN101989837B GaAs HBT high-gain broadband linear transconductance unit circuit |
| 08/07/2013 | CN101904100B Replica bias circuit for high speed low voltage common mode driver |
| 08/06/2013 | US8504950 Modular array defined by standard cell logic |
| 08/06/2013 | US8502564 Adjustable Schmitt trigger |
| 08/06/2013 | US8502563 Non-binary decoder architecture and control signal logic for reduced circuit complexity |
| 08/06/2013 | US8502562 Buffering circuit, semiconductor device having the same, and methods thereof |
| 08/06/2013 | US8502561 Signal value storage circuitry with transition detector |
| 08/06/2013 | US8502560 Output circuit and output control system |
| 08/06/2013 | US8502559 Level translator |
| 08/06/2013 | US8502557 Apparatus and methods for forming electrical networks that approximate desired performance characteristics |
| 08/06/2013 | US8502556 System and method for reducing input current spike for drive circuitry |
| 08/06/2013 | US8502555 Method of and circuit for preventing the alteration of a stored data value |
| 08/01/2013 | WO2013110771A1 Switching circuit and method |
| 08/01/2013 | US20130194003 Driver circuit |
| 08/01/2013 | US20130194002 Re-configurable mixed-mode integrated circuit architecture |
| 08/01/2013 | US20130194001 Data output circuit |
| 08/01/2013 | US20130193999 Sequential circuit with current mode error detection |
| 07/31/2013 | EP2621090A1 Switching circuit and method |
| 07/31/2013 | EP2620833A1 Clock gating system and method |
| 07/31/2013 | EP2619908A1 System for accomplishing bi-directional digital audio data and control communications |
| 07/31/2013 | EP2619907A1 Incorporating an independent logic block in a system-on-a-chip |
| 07/31/2013 | CN203104404U Mining intrinsic safety information transmission interface |
| 07/31/2013 | CN203104403U 75110 chip driving photocoupler circuit |
| 07/31/2013 | CN203104402U Source electrode follower based on deep N-well NMOS (N-channel Metal Oxide Semiconductor) transistor |
| 07/31/2013 | CN203104401U Level converting circuit and low voltage differential circuit |
| 07/31/2013 | CN203104400U Switch cabinet lightning arrester monitoring system and communication interface therein |
| 07/31/2013 | CN203104399U Signal conditioning circuit |
| 07/31/2013 | CN203104398U Power ultrasonic driver |
| 07/31/2013 | CN203104397U Current maintaining circuit |
| 07/31/2013 | CN203104396U Servo loop of flexible gyroscope |
| 07/31/2013 | CN203104395U Integrator circuit |
| 07/31/2013 | CN1610261B Programmable phase-locked loop circuitry for programmable logic device |
| 07/31/2013 | CN103227636A High-isolation direct splicing half-duplex communication interface module for interconnection of multiple controllers |
| 07/31/2013 | CN103227635A High-speed and low-power-consumption CMOS full adder and operation method thereof |
| 07/31/2013 | CN103227634A Low-power dissipation USB (Universal Serial Bus) high-speed signal level conversion circuit |
| 07/31/2013 | CN103227633A High-speed-mode signal detection circuit |
| 07/31/2013 | CN103227632A 1-in-16 data selection circuit based on Lipschitz Exponent restricting competition counting and coding |
| 07/31/2013 | CN102497193B High-precision zero drift compensation circuit for analog multiplier |
| 07/31/2013 | CN102263550B 逻辑信号传送电路 A logic signal transmission circuit |
| 07/30/2013 | US8499269 Timing exact design conversions from FPGA to ASIC |
| 07/30/2013 | US8497707 Transmitter equalization method and circuit using unit-size and fractional-size subdrivers in output driver for high-speed serial interface |
| 07/30/2013 | US8497706 Adjustable data drivers and methods for driving data signals |
| 07/30/2013 | US8497705 Phase change device for interconnection of programmable logic device |
| 07/30/2013 | US8497704 Methods and structure for source synchronous circuit in a system synchronous platform |
| 07/30/2013 | US8497702 Power control of an integrated circuit including an array of interconnected configurable logic elements |
| 07/30/2013 | US8497700 Systems and methods for propagating digital data across an isolation barrier |
| 07/30/2013 | US8497699 Output driver robust to data dependent noise |
| 07/25/2013 | WO2013110019A1 Transition time lock loop with reference on request |
| 07/25/2013 | WO2013109693A1 Slew-rate limited output driver with output-load sensing feedback loop |
| 07/25/2013 | WO2013109578A1 Rail-to-rail input circuit |
| 07/25/2013 | WO2013108505A1 Physical quantity detection device |
| 07/25/2013 | US20130187703 Symmetrically operating single-ended input buffer devices and methods |
| 07/25/2013 | US20130187699 Techniques for switching between ac-coupled connectivity and dc-coupled connectivity |
| 07/25/2013 | US20130187686 Flip-flop circuit, frequency divider and frequency dividing method |
| 07/25/2013 | US20130187680 Complementary Logic Device Comprising Metal-to-Insulator Transition Material |
| 07/25/2013 | US20130187679 Enhanced performance memory systems and methods |
| 07/24/2013 | EP2618489A1 Output buffer circuit |
| 07/24/2013 | EP2618486A2 A method and apparatus for driving a voltage controlled power switch device |
| 07/24/2013 | CN203086439U High-resistance signal-interference-preventing type photoelectric coupler |
| 07/24/2013 | CN203086438U Signal processing circuit |
| 07/24/2013 | CN203086437U Level switching circuit |
| 07/24/2013 | CN203086436U Integrated circuit |
| 07/24/2013 | CN203086435U Bilateral signal isolation transmission system |
| 07/24/2013 | CN203086434U Key control circuit for single-battery power supply system |
| 07/24/2013 | CN203086426U CMOS delay circuit |
| 07/24/2013 | CN103222194A Level-shift circuit using resistance of semiconductor substrate |
| 07/24/2013 | CN103219991A Dynamic reconfigurable logic gate realization method based on cellular neural network (CNN) and realization circuit thereof |
| 07/24/2013 | CN103219990A Three-value low power consumption T-operational circuit based on adiabatic domino logic |
| 07/24/2013 | CN103219989A High-linearity sigma-delta closed loop accelerometer interface circuit |
| 07/24/2013 | CN103219988A Method for automatically identifying pluggable audio devices and terminal |
| 07/24/2013 | CN103219987A Current or voltage sensor signal collection protective circuit |
| 07/24/2013 | CN103219986A Polarity insensitive transmit-receive unit and RS-485 communication circuit |
| 07/24/2013 | CN103219985A System and method of power distribution control of an integrated circuit |
| 07/24/2013 | CN103219984A Numerical-field clock recovery generating device |
| 07/24/2013 | CN103219983A Memristor equivalent simulation circuit |
| 07/24/2013 | CN103219982A Asynchronous signal synchronization circuit based on double sampling |
| 07/24/2013 | CN102355253B Output stage circuit used for outputting driving current changing along with technology |
| 07/24/2013 | CN102034553B Shift register and gate line driving device thereof |
| 07/23/2013 | US8495550 Soft error hard electronic circuit and layout |
| 07/23/2013 | US8495122 Programmable device with dynamic DSP architecture |
| 07/23/2013 | US8493106 Semiconductor device and method for controlling flip-flop |
| 07/23/2013 | US8493093 Time division multiplexed limited switch dynamic logic |
| 07/23/2013 | US8493092 Linear equalizer |
| 07/23/2013 | US8493091 Programmable logic device |
| 07/23/2013 | US8493088 Dynamic voltage and frequency management |
| 07/18/2013 | WO2013106687A2 Multi-threshold sleep convention logic without nsleep |
| 07/18/2013 | WO2013106091A1 Driver circuit and method of generating an output signal |
| 07/18/2013 | WO2013105388A1 Bi-directional buffer and control method thereof |
| 07/18/2013 | WO2013078294A3 Layouts for memory and logic circuits in a system-on-chip |
| 07/18/2013 | US20130182513 Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device |
| 07/18/2013 | US20130181763 Level shifter |
| 07/18/2013 | US20130181743 Binary Logic Unit and Method to Operate a Binary Logic Unit |
| 07/18/2013 | US20130181742 Method and apparatus to serialize parallel data input values |