Patents
Patents for H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate (229,248)
02/2008
02/26/2008US7335569 In-situ formation of metal insulator metal capacitors
02/26/2008US7335568 Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same
02/26/2008US7335561 Semiconductor integrated circuit device and manufacturing method thereof
02/26/2008US7335560 Methods of forming a nonvolatile memory device having a local SONOS structure that uses spacers to adjust the overlap between a gate electrode and a charge trapping layer
02/26/2008US7335557 Semiconductor device of non-volatile memory
02/26/2008US7335552 Electrode for thin film capacitor devices
02/26/2008US7335550 Methods for forming semiconductor devices including thermal processing
02/26/2008US7335549 Semiconductor device and method for fabricating the same
02/26/2008US7335545 Control of strain in device layers by prevention of relaxation
02/26/2008US7335540 Low temperature polysilicon thin film transistor and method of manufacturing the same
02/26/2008US7335533 Methods for assembling semiconductor devices in superimposed relation with adhesive material defining the distance adjacent semiconductor devices are spaced apart from one another
02/26/2008US7335528 Methods of nanotube films and articles
02/26/2008US7335518 Method for manufacturing semiconductor device
02/26/2008US7335255 Manufacturing method of semiconductor device
02/26/2008US7334320 Method of making an electronic fuse with improved ESD tolerance
02/21/2008WO2008022166A2 Open source/drain junction field effect transistor
02/21/2008WO2008021912A2 Nonvolatile resistive memories, latch circuits, and operation circuits having scalable two-terminal nanotube switches
02/21/2008WO2008021911A2 Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks
02/21/2008WO2008021736A2 Nonvolatile memories with shaped floating gates
02/21/2008WO2008021554A2 A configurable decoder with applications in fpgas
02/21/2008WO2008021362A1 Memory device with non-orthogonal word and bit lines and manufacturing method thereof
02/21/2008WO2008020899A2 Arrayed imaging systems and associated methods
02/21/2008WO2008020692A1 Pixel for picking up image signal and method of manufacturing the pixel
02/21/2008WO2008020566A1 Semiconductor device, semiconductor device manufacturing method and display device
02/21/2008WO2008020396A1 Electroluminescent device having a variable color point
02/21/2008WO2008019616A1 Electrical thin film memory
02/21/2008WO2008001957B1 Display apparatus and information processing apparatus using the same
02/21/2008WO2007149515A3 Floating gate memory devices and fabrication
02/21/2008WO2007145790A9 An integrated circuit device having barrier and method of fabricating the same
02/21/2008WO2007119321A3 Light-emitting device using oxide semiconductor thin-film transistor and image display apparatus using the same
02/21/2008WO2001001452A3 Organic light emitters with improved carrier injection
02/21/2008US20080046759 ID installable LSI, secret key installation method, LSI test method, and LSI development method
02/21/2008US20080046636 Monolithic read-while-write flash memory device
02/21/2008US20080045023 Method for manufacturing semiconductor device, and semiconductor device
02/21/2008US20080045008 Post passivation interconnection schemes on top of IC chip
02/21/2008US20080045004 Post passivation interconnection schemes on top of IC chips
02/21/2008US20080045002 Post passivation interconnection schemes on top of IC chip
02/21/2008US20080045001 Post passivation interconnection schemes on top of IC chip
02/21/2008US20080044996 Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof
02/21/2008US20080044994 Semiconductor device capable of threshold voltage adjustment by applying an external voltage
02/21/2008US20080044983 Element formation substrate, method of manufacturing the same, and semiconductor device
02/21/2008US20080044977 High performance system-on-chip using post passivation process
02/21/2008US20080044976 High performance system-on-chip using post passivation process
02/21/2008US20080044969 Turn-on-efficient bipolar structures with deep n-well for on-chip esd protection
02/21/2008US20080044963 Tft substrate for liquid crystal display apparatus and method of manufacturing the same
02/21/2008US20080044961 Thin film transistor array panel
02/21/2008US20080044954 Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby
02/21/2008US20080044940 Laminating System
02/21/2008US20080044930 Transplanted magnetic random access memory (mram) devices on thermally-sensitive substrates using laser transfer and method of making the same
02/21/2008US20080044669 Method for Manufacturing Simox Substrate and Simox Substrate Obtained by the Method
02/21/2008US20080043530 Non-volatile semiconductor memory adapted to store a multi-valued data in a single memory cell
02/21/2008US20080043529 Novel Multi-State Memory
02/21/2008US20080043526 Operating Techniques for Reducing Program and Read Disturbs of a Non-Volatile Memory
02/21/2008US20080043389 Circuit Arrangement and Method for the Protection of a Circuit Against Electrostatic Discharges
02/21/2008US20080043127 Solid-state image pickup device and method of producing the same
02/21/2008US20080043045 Image display device and method of manufacturing the same
02/21/2008US20080042687 Programmable Logic Device and Method for Designing the Same
02/21/2008US20080042584 Method of manufacturing thin film transistor
02/21/2008US20080042296 Post passivation interconnection schemes on top of the IC Chips
02/21/2008US20080042295 Post passivation interconnection schemes on top of IC chip
02/21/2008US20080042294 Post passivation interconnection schemes on top of IC chip
02/21/2008US20080042293 Post passivation interconnection schemes on top of IC chip
02/21/2008US20080042289 High performance system-on-chip using post passivation process
02/21/2008US20080042287 Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers
02/21/2008US20080042285 Post passivation interconnection schemes on top of IC chip
02/21/2008US20080042282 Semiconductor integrated circuit device and a method of manufacturing the same
02/21/2008US20080042273 High performance system-on-chip using post passivation process
02/21/2008US20080042239 High performance system-on-chip using post passivation process
02/21/2008US20080042238 High performance system-on-chip using post passivation process
02/21/2008US20080042237 Semiconductor device and method of manufacturing the same
02/21/2008US20080042227 Solid-Stated Image Pickup Device And Method For Manufacturing Same
02/21/2008US20080042217 Array substrate for a liquid crystal display device and manufacturing method of the same
02/21/2008US20080042214 Semiconductor device
02/21/2008US20080042212 Printed dopant layers
02/21/2008US20080042206 Integrated circuit device having input/output electrostatic discharge protection cell equipped with electrostatic discharge protection element and power clamp
02/21/2008US20080042204 Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
02/21/2008US20080042203 Single and double-gate pseudo-fet devices for semiconductor materials evaluation
02/21/2008US20080042202 QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS
02/21/2008US20080042199 Open source/drain junction field effect transistor
02/21/2008US20080042193 Semiconductor device
02/21/2008US20080042182 Capacitor and method of manufacturing the same
02/21/2008US20080042181 Semiconductor device
02/21/2008US20080042180 Semiconductor Device
02/21/2008US20080042175 Solid state image pickup device and method of producing solid state image pickup device
02/21/2008US20080042171 Transistor arrangement, sense-amplifier arrangement and methods of manufacturing the same via a phase shift mask
02/21/2008US20080042170 Image Sensor and Method for Manufacturing the Same
02/21/2008US20080042168 Laminating System, Ic Sheet, Scroll of Ic Sheet, and Method for Manufacturing Ic Chip
02/21/2008US20080042167 Phase change materials and associated memory devices
02/21/2008US20080042154 Light-emitting device, method of fabricating the same, and electronic apparatus
02/21/2008US20080042152 Electronic device, display device, interface circuit and differential amplification device, which are constituted by using thin-film transistors
02/21/2008US20080042137 Electro-optical device, method for manufacturing electro-optical device, and electronic apparatus
02/21/2008US20080042135 Thin-film transistor substrate, method of manufacturing the same and display apparatus having the same
02/21/2008US20080042126 Ballistic direct injection NROM cell on strained silicon structures
02/21/2008US20080042120 Integrated circuit device, manufacturing method thereof, and display device
02/21/2008US20080042066 Method and Apparatus for Increasing Light Absorption in an Image Sensor Using Energy Conversion Layer
02/21/2008US20080042048 Digital-to-analog converter, analog-to-digital converter, and semiconductor device
02/21/2008US20080042047 Cmos image sensor and related method of operation
02/21/2008US20080042046 Physical quantity detection device, method of driving physical quantity detection device, and imaging apparatus
02/21/2008DE10392392B4 Verfahren zur Herstellung einer integrierten Schaltung mit nichtflüchtigem Speicherbauelement ohne Bitleitungskurzschlüsse A method of manufacturing an integrated circuit nonvolatile memory device without Bitleitungskurzschlüsse
02/21/2008DE102006038899A1 Solid electrolyte memory cell has optional access and solid electrolyte block with three solid electrolyte contact areas, where electrodes are electrically connected with contact areas, which are spatially separated from each other