Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
08/2012
08/14/2012US8244938 Sliding write window mechanism for writing data
08/14/2012US8244937 Solid state storage device controller with parallel operation mode
08/14/2012US8244936 Data communication apparatus for stabilizing the connection of a communication line between data communication apparatuses and program therefor
08/14/2012US8244934 Data storage network management
08/14/2012US8244925 Circuit board and liquid crystal display includes changing EDID information
08/14/2012US8244783 Normalizer shift prediction for log estimate instructions
08/09/2012WO2012106108A1 System and method for managing a memory as a circular buffer
08/09/2012US20120202529 Intelligent Network Interface System and Method for Accelerated Protocol Processing
08/08/2012CN102117193B Method for implementing pre-read FIFO and pre-read FIFO
08/07/2012US8239592 Smart card with self-detachment features and related methods
08/07/2012US8239586 Method and apparatus for interfacing with multiple objects using an object independent interface protocol
08/07/2012US8239158 Synchronizing a loop performed by a measurement device with a measurement and control loop performed by a processor of a host computer
08/07/2012US8239087 Method of operating a vehicle accessory
08/07/2012US8239049 Playing state presentation system, playing state presentation device, playing state presentation method, and playing state presentation program
08/02/2012US20120197954 Floating point multiplier circuit with optimized rounding calculation
08/02/2012US20120197953 Montgomery inverse calculation device and method of calculating montgomery inverse using the same
07/2012
07/31/2012US8234661 Secure digital input/output interface system
07/31/2012US8234587 System for accessing a large number of menu items using a zoned menu bar
07/31/2012US8234470 Data repository selection within a storage environment
07/31/2012US8234422 Interfaces, circuits, and methods for communicating with a double data rate memory device
07/31/2012US8234421 Smart card with selectively allocatable data buffers and associated methods
07/31/2012US8234420 Method, system, and apparatus for communicating using multiple controllers
07/31/2012US8234361 Computerized system and method for handling network traffic
07/26/2012US20120192283 Interlocked Binary Protection Using Whitebox Cryptography
07/25/2012CN102609235A Method and system for updating data after data reading of double-port RAM (random-access memory)
07/25/2012CN102609234A FIFO (first in, first out) circuit capable of adjusting size of memory cells
07/25/2012CA2764660A1 Formatting data
07/24/2012US8230066 Location independent backup of data from mobile and stationary computers in wide regions regarding network and server activities
07/24/2012US8230043 Documentation process for invoking help from a server
07/18/2012CN102591843A Inter-core communication method for multi-core processor
07/17/2012US8225033 Data storage system, electronic system, and telecommunications system
07/11/2012EP2474129A1 Data broker method, apparatus and system
07/11/2012EP1894089B1 Data pipeline management system and method for using the system
07/11/2012CN102576301A Interfacing circuit comprising a fifo storage
07/10/2012US8220000 System and method for executing files stored in logical units based on priority and input/output load of the logical units
07/10/2012US8219715 Multi-pathing with SCSI I/O referrals
07/04/2012EP1188162B1 Data transfer apparatus and data transfer method with double buffering
07/04/2012CN102541506A First-in-first-out (FIFO) data register, chip and equipment
07/04/2012CN101788898B Memory controller
07/04/2012CN101558451B Circuit with parallel functional circuits with multi-phase control inputs
07/04/2012CN101095101B Memory controller-adaptive 1t/2t timing control
07/03/2012US8214668 Synchronizing circuit
07/03/2012US8214562 Processing of data to perform system changes in an input/output processing system
07/03/2012US8214559 Virtual machine system
07/03/2012US8214557 Measuring direct memory access throughput
07/03/2012US8214553 Virtualization of an input/output device for supporting multiple hosts and functions
06/2012
06/28/2012WO2012084835A1 Buffer management scheme for a network processor
06/27/2012CN102520902A Parallel write-in multi-FIFO (first in,first out) implementation method based on single chip block RAM (random access memory)
06/27/2012CN101208675B Frame order processing apparatus, systems, and methods
06/26/2012US8209703 Apparatus and method for dataflow execution in a distributed environment using directed acyclic graph and prioritization of sub-dataflow tasks
06/26/2012US8209444 Keyboards providing macro functions and macro function setting method using the same, and computer program products thereof
06/20/2012EP2466451A1 Method for controlling operation of a memory, corresponding system, and computer program product
06/20/2012CN102508631A Written data processing device of first input first output (FIFO) for writing any byte data
06/19/2012US8205111 Communicating via an in-die interconnect
06/14/2012WO2012076391A1 Vector gather buffer for multiple address vector loads
06/14/2012US20120150932 Divider circuit and division method
06/14/2012DE102010062567A1 Verfahren, Sensormodul und System zur Datenübertragung Method, the sensor module and system for data transmission
06/13/2012CN102495713A Method and system for realizing asynchronous first in first out (FIFO) of any depth
06/12/2012US8201011 Timing optimization for paths in a processor
06/12/2012US8200870 Switching serial advanced technology attachment (SATA) to a parallel interface
06/12/2012US8200367 Bulk material transport system
06/07/2012WO2012072862A1 Method and apparatus for predicting and pre-fetching location information
06/07/2012US20120144155 System Of Rotating Data In A Plurality Of Processing Elements
06/07/2012US20120144074 Interfacing Circuit Comprising a FIFO Storage
06/07/2012US20120139928 Data packer for packing and aligning write data
05/2012
05/31/2012US20120137349 Safe application distribution and execution in a wireless environment
05/30/2012EP2457168A1 Signal processing system, integrated circuit comprising buffer control logic and method therefor
05/30/2012EP2457150A1 Interfacing circuit comprising a fifo storage
05/30/2012CN102483790A 利用白盒密码术的联锁二进制保护 Use white-box cryptography binary interlock protection
05/30/2012CN101782843B Decomposition method and decomposition circuit for barrel shifter, and control method thereof
05/30/2012CN101292221B Encoding for serial link based on signal transition characteristic
05/29/2012US8190924 Computer system, processor device, and method for controlling computer system
05/29/2012US8190794 Control function for memory based buffers
05/29/2012US8190783 Assigning input devices to specific sessions
05/24/2012US20120131241 Signal processing system, integrated circuit comprising buffer control logic and method therefor
05/24/2012US20120131240 Sliding write window mechanism for writing data
05/24/2012US20120131087 Concurrently applying an image file while it is being downloaded using a multicast protocol
05/24/2012US20120131078 Arithmetic device
05/23/2012EP1540507B1 Device for processing data with an array of reconfigurable elements
05/23/2012CN102473149A Signal processing system, integrated circuit comprising buffer control logic and method therefor
05/23/2012CN101110015B Data reversal bucket shaped shift method based on mask code
05/22/2012US8185675 Interface system and operating method thereof
05/17/2012US20120124117 Fused multiply-add apparatus and method
05/15/2012US8180931 USB-attached-SCSI flash-memory system with additional command, status, and control pipes to a smart-storage switch
05/15/2012US8180714 Automatic generation of human models for motion capture, biomechanics and animation
05/10/2012US20120117135 Method for generating a sequence in a wireless communication system, and apparatus for same
05/09/2012CN102446085A Hardware accelerator module and method for setting up same
05/09/2012CN102446084A Write-read control method and device of timing information
05/08/2012US8176492 Synchronous adaption of asynchronous modules
05/03/2012US20120110224 Data processing apparatus and image processing apparatus
05/03/2012US20120110223 Lock-less buffer management scheme for telecommunication network applications
05/03/2012US20120110222 Apparatus and method for dynamically enabling and disabling write xfr_rdy
05/01/2012US8171334 Apparatus and method to interface two different clock domains
05/01/2012US8171332 Integrated circuit with reduced electromagnetic interference induced by memory access and method for the same
05/01/2012US8171189 Semiconductor apparatus
05/01/2012US8171188 Method of handling successive bitstream extraction and packing and related device
04/2012
04/26/2012US20120102243 Method for the recovery of a clock and system for the transmission of data between data memories by remote direct memory access and network station set up to operate in the method as a transmitting or,respectively,receiving station
04/24/2012US8166215 Method to control delay between lanes
04/24/2012US8166214 Shared storage for multi-threaded ordered queues in an interconnect
04/24/2012US8166213 Controller with indirect accessible memory
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ... 82