Patents
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
11/1977
11/08/1977US4057846 Bus steering structure for low cost pipelined processor system
11/01/1977US4056847 Priority vector interrupt system
11/01/1977US4056846 Data processing system with apparatus for sharing channel background processing
11/01/1977US4056843 Data processing system having a plurality of channel processors
10/1977
10/25/1977US4055851 Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
10/25/1977US4055835 Line-seizing apparatus
10/18/1977US4054949 Stagnation prevention apparatus in an information transmission system
10/11/1977US4053950 Residual status reporting during chained cycle steal input/output operations
10/04/1977US4052702 Circuit for interfacing microcomputer to peripheral devices
09/1977
09/20/1977US4050097 Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus
09/20/1977US4050096 Pulse expanding system for microprocessor systems with slow memory
09/20/1977US4050058 Microprocessor with parallel operation
09/20/1977US4049974 Precharge arithmetic logic unit
09/13/1977US4048673 O bus interface for a data processing system
09/13/1977US4048672 Switch matrix control and display
09/13/1977US4048623 Data processing system
09/13/1977US4048446 Data transmission system
09/06/1977US4047246 O bus transceiver for a data processing system
09/06/1977US4047201 I/O Bus transceiver for a data processing system
09/06/1977US4047162 Interface circuit for communicating between two data highways
09/06/1977US4047159 Data transmission systems
09/06/1977US4047158 Peripheral processing system
09/06/1977US4047157 Secondary storage facility for data processing
08/1977
08/30/1977US4045782 Microprogrammed processor system having external memory
08/30/1977US4045684 Information transfer bus circuit with signal loss compensation
08/23/1977US4044333 Data processing switching system
08/16/1977US4042913 Address key register load/store instruction system
08/16/1977US4042783 Method and apparatus for byte and frame synchronization on a loop system coupling a CPU channel to bulk storage devices
08/16/1977US4042780 Multiple message frame adaptor apparatus for loop communication system
08/09/1977US4041473 Computer input/output control apparatus
08/09/1977US4041472 Data processing internal communications system having plural time-shared intercommunication buses and inter-bus communication means
08/02/1977US4040037 Buffer chaining
08/02/1977US4040032 Peripheral device controller for a data processing system
08/02/1977US4040028 Output processors
08/02/1977US4040027 Digital data transfer system having delayed information readout from a first memory into a second memory
08/02/1977US4040026 Channel for exchanging information between a computer and rapid peripheral units
07/1977
07/26/1977US4038644 Destination selection apparatus for a bus oriented computer system
07/26/1977US4038642 Input/output interface logic for concurrent operations
07/26/1977US4038641 Output interrupt or cycle steal data transfer requests
07/19/1977US4037210 Computer-peripheral interface
07/19/1977US4037094 Multi-functional arithmetic and logical unit
07/12/1977US4035780 Priority interrupt logic circuits
07/12/1977US4035777 Data processing system including parallel bus transfer control port
07/05/1977US4034351 Method and apparatus for transmitting common information in the information processing system
07/05/1977US4034349 Apparatus for processing interrupts in microprocessing systems
07/05/1977US4034347 Method and apparatus for controlling a multiprocessor system
07/05/1977US4034346 Interface for establishing communications between a data-processing unit and a plurality of stations
06/1977
06/28/1977US4032898 Interface control unit for transferring sets of characters between a peripheral unit and a computer memory
06/21/1977US4031518 Data capture terminal
06/21/1977US4031317 Data communications system with improved digital phase-locked loop retiming circuit
06/14/1977US4030076 O devices
06/14/1977US4030075 Data processing system having distributed priority network
06/14/1977US4030073 Initialization circuit for establishing initial operation of a digital computer
06/07/1977US4028682 Circuit arrangement for selecting the function of connection contacts on circuit chips
06/07/1977US4028675 Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
06/07/1977US4028668 Apparatus for selectively addressing sections and locations in a device controller's memory
06/07/1977US4028665 Information store system comprising a plurality of different shift-registers
06/07/1977US4028664 Apparatus for dispatching data of the highest priority process having the highest priority channel to a processor
06/07/1977US4028663 Digital computer arrangement for high speed memory access
05/1977
05/31/1977USRE29246 Data transfer control apparatus and method
05/31/1977US4027290 Peripherals interrupt control unit
05/31/1977US4027152 Apparatus and method for transmitting binary-coded information
05/24/1977US4025906 Apparatus for identifying the type of devices coupled to a data processing system controller
05/17/1977US4024505 Interface system for coupling an indeterminate number of peripheral devices to a central processing unit
05/10/1977US4023143 Fixed priority interrupt control circuit
05/03/1977US4021784 Clock synchronization system
04/1977
04/26/1977US4020472 Master slave registers for interface adaptor
04/26/1977US4020471 Interrupt scan and processing system for a data processing system
04/26/1977US4020466 Memory hierarchy system with journaling and copy back
04/19/1977US4019176 System and method for reliable communication of stored messages among stations over a single common channel with a minimization of service message time
04/12/1977US4017841 Bus allocation control apparatus
04/12/1977US4017840 Method and apparatus for protecting memory storage location accesses
04/12/1977US4017839 Output multiplexer security system
04/12/1977US4017829 Method and circuit arrangement for testing data processors
04/12/1977US4017740 Synchronization of digital circuits by bus triggering
04/05/1977US4016548 Communication multiplexer module
04/05/1977US4016541 Memory unit for connection to central processor unit and interconnecting bus
04/05/1977US4016540 Apparatus and method for providing interactive audio communication
04/05/1977US4016539 Asynchronous arbiter
04/05/1977US4016367 Communication multiplexer module
03/1977
03/29/1977US4015246 Synchronous fault tolerant multi-processor system
03/29/1977US4015244 Selective addressing system
03/29/1977US4015243 Multi-processing computer system
03/29/1977US4015241 Information processing system
03/22/1977US4014006 Data processing system having a unique cpu and memory tuning relationship and data path configuration
03/22/1977US4014005 Configuration and control unit for a heterogeneous multi-system
03/15/1977US4012719 Communication multiplexer module
03/15/1977US4012718 Communication multiplexer module
03/15/1977US4012593 Bidirectional repeater in data transmission system
03/08/1977US4011465 Metal oxide semiconductors, field effect transistors
03/01/1977US4010448 Interrupt circuitry for microprocessor chip
03/01/1977US4010326 Line selective time division communication system
02/1977
02/22/1977US4009471 Information transfer system
02/22/1977US4009470 Pre-emptive, rotational priority system
02/22/1977US4009469 Loop communications system with method and apparatus for switch to secondary loop
02/08/1977US4007450 Data sharing computer network
02/08/1977US4007449 Control device for local connection of a peripheral unit through a modem interface for remote connection
02/08/1977US4007448 Drive for connection to multiple controllers in a digital data secondary storage facility
02/08/1977US4007441 Method of data communications in a heterogenous environment
02/08/1977US4007329 Data communications system with improved asynchronous retiming circuit