Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 11 - Error detection; Error correction; Monitoring
Patents for G06F 11 - Error detection; Error correction; Monitoring (140,345)
06/1995
06/29/1995CA2179523A1 Method and apparatus for implementing user feedback
06/29/1995CA2179298A1 Information display system for actively redundant computerized process control
06/28/1995EP0660534A2 Error correction systems with modified viterbi decoding
06/28/1995EP0660259A2 Joy stick type operating lever device
06/28/1995EP0660236A1 Disc array system having disc storage devices dispersed on plural boards and accessible at withdrawal of part of the boards
06/28/1995EP0660235A1 Method for automated software application testing
06/28/1995CN1104355A Inter-section cross cable detection system
06/28/1995CN1104354A Virus-proof method for universal network
06/27/1995US5428802 For use in a disk data storage and retrieval system
06/27/1995US5428795 Method of and apparatus for providing automatic security control of distributions within a data processing system
06/27/1995US5428788 Feature ratio method for computing software similarity
06/27/1995US5428770 Single-chip microcontroller with efficient peripheral testability
06/27/1995US5428768 System for checking comparison check function of information processing apparatus
06/27/1995US5428767 Data retention circuit
06/27/1995US5428766 Error detection scheme in a multiprocessor environment
06/27/1995US5428745 Secure communication system for re-establishing time limited communication between first and second computers before communication time period expiration using new random number
06/27/1995US5428630 System and method for verifying the integrity of data written to a memory
06/27/1995US5428628 Modular implementation for a parallelized key equation solver for linear algebraic codes
06/27/1995US5428627 Method and apparatus for initializing an ECC circuit
06/27/1995US5428624 Fault injection using boundary scan
06/27/1995US5428623 Scannable interface to nonscannable microprocessor
06/27/1995US5428621 Latent defect handling in EEPROM devices
06/27/1995US5428619 Model based reasoning system for network fault diagnosis
06/27/1995US5428618 Debugger apparatus and method having an event history recording capability
06/27/1995US5428571 Data latch circuit having non-volatile memory cell equipped with common floating gate and stress relaxing transistor
06/22/1995WO1995016953A1 Processor system and debug mode accomplishment method
06/22/1995WO1995016949A1 Automatic gathering and graphical display of useability test data
06/22/1995WO1995016940A1 Data processing medium, its backup circuit, and data processing system
06/22/1995WO1995016924A1 Device for testing the connection between an output of a means which outputs a fixed logic value and the input of a circuit
06/22/1995DE4445444A1 Distributed database management system for network access
06/22/1995DE4341959A1 Integrated circuit with improved wiring
06/22/1995CA2156058A1 Automatic gathering and graphical display of useability test data
06/21/1995EP0658896A2 Apparatus and methods for improving data detection reliability
06/21/1995EP0658845A1 Method and apparatus to store transaction data
06/21/1995EP0658844A2 Central processing unit using dual basic processing units and verification using accumulated results comparison
06/21/1995EP0658843A1 Method for hibernation file creation
06/21/1995EP0658842A1 Watch dog timer device
06/21/1995EP0658257A1 Communications control unit and information transmission process.
06/21/1995EP0622744B1 Method and system for determining the composition of an integrated circuit
06/21/1995EP0390892B1 Activity verification system for memory or logic
06/21/1995EP0306244B1 Fault tolerant computer system with fault isolation
06/21/1995EP0287302B1 Cross-coupled checking circuit
06/20/1995US5426778 Computer system for shifting an operation timing thereof in response to a detected abnormal states
06/20/1995US5426776 Microprocessor watchdog circuit
06/20/1995US5426774 Method for maintaining a sequence of events function during failover in a redundant multiple layer system
06/20/1995US5426768 Logic simulation with efficient deadlock avoidance by selectively suspending event data fetch based on element information
06/20/1995US5426767 Method for distinguishing between a 286-type central processing unit and a 386-type central processing unit
06/20/1995US5426759 On-chip/off-chip memory switching using system configuration bit
06/20/1995US5426746 Microcontroller with program recomposing function
06/20/1995US5426744 Single chip microprocessor for satisfying requirement specification of users
06/20/1995US5426741 Bus event monitor
06/20/1995US5426654 Channel data CRC systems for use with cross connect equipment
06/20/1995US5426652 Data reception technique
06/20/1995US5426649 Test interface for a digital circuit
06/20/1995US5426648 Efficient program debugging system
06/20/1995US5426646 Instantaneous bit-error-rate meter
06/20/1995CA2043555C Method for modifying a fault-tolerant processing system
06/15/1995WO1995016237A1 Incremental backup system
06/14/1995EP0657822A1 Multi-access limiting circuit for a multi-memory device
06/14/1995EP0657816A1 Computer with a status indicator unit
06/14/1995EP0657813A1 Distributed database management
06/14/1995EP0657812A1 System and method for monitoring library software
06/14/1995EP0657046A1 Fault tolerant three port communications module.
06/14/1995EP0657045A1 Script-based system for testing a multi-user computer system
06/14/1995EP0610316B1 Process and device for dealing with errors in electronic control devices
06/14/1995EP0419734B1 Method for testing a hierarchically organised integrated circuit device, and integrated circuit device suitable for being so tested
06/14/1995CN1103748A Method for executing software program and circuit device for implementing the method
06/13/1995US5425038 Error plus single bit error detection
06/13/1995US5425035 Enhanced data analyzer for use in bist circuitry
06/13/1995US5425034 Semiconductor integrated logic circuit with internal circuit to be examined by scan path test method
06/13/1995US5425033 Detection of errors in a digital transmission system
06/08/1995WO1995015630A1 Network interface unit remote test pattern generation
06/08/1995WO1995015529A1 Fault resilient/fault tolerant computing
06/08/1995WO1995006277A3 Separately clocked processor synchronization improvement
06/08/1995DE4340899A1 Meßvorrichtung zum Testen der Verbindungen zwischen wenigstens zwei Baugruppen Measuring device for testing the connections between at least two modules
06/08/1995CA2177850A1 Fault resilient/fault tolerant computing
06/07/1995EP0656712A1 Viterbi equaliser using variable length tracebacks
06/07/1995EP0656658A1 High density memory structure
06/07/1995EP0656591A1 ATE system with integrated bus simulation
06/07/1995EP0656590A2 Measuring device to test the connection between at least two subassemblies
06/07/1995EP0656589A2 Digital image forming apparatus
06/07/1995EP0352340B1 Method for monitoring the operating environment of a computer system
06/06/1995USH1444 VME slave tester
06/06/1995US5423046 High capacity data storage system using disk array
06/06/1995US5423037 Continuously available database server having multiple groups of nodes, each group maintaining a database copy with fragments stored on multiple nodes
06/06/1995US5423030 Bus station abort detection
06/06/1995US5423029 Circuit and method for testing direct memory access circuitry
06/06/1995US5423028 Diagnostic procedure for identifying presence of computer memory
06/06/1995US5423027 Tool for error detection in software using aspect specification
06/06/1995US5423026 Method and apparatus for performing control unit level recovery operations
06/06/1995US5423025 Error handling mechanism for a controller having a plurality of servers
06/06/1995US5423024 Fault tolerant processing section with dynamically reconfigurable voting
06/06/1995US5422915 Fault tolerant clock distribution system
06/06/1995US5422896 Timing check circuit for a functional macro
06/06/1995US5422893 Maintaining information from a damaged frame by the receiver in a communication link
06/06/1995US5422891 Robust delay fault built-in self-testing method and apparatus
06/06/1995US5422890 Method for dynamically measuring computer disk error rates
06/06/1995US5422877 Dual bus switching
06/06/1995US5422847 Non-volatile memory controlling apparatus
06/06/1995US5422837 Apparatus for detecting differences between double precision results produced by dual processing units operating in parallel
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