| Patents for G06F 17 - Digital computing or data processing equipment or methods, specially adapted for specific functions (471,733) |
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| 08/24/2006 | WO2006086912A1 Transportation path querying system |
| 08/24/2006 | WO2006086846A1 Methods of genetic analysis involving the amplification of complementary duplicons |
| 08/24/2006 | WO2006073928A3 Computer networked game system utilizing subscription based membership and alternative methods of entry |
| 08/24/2006 | WO2006072882A3 Embedded translation-enhanced search |
| 08/24/2006 | WO2006071928A9 Routing queries to information sources and sorting and filtering query results |
| 08/24/2006 | WO2006071258A3 Systems and methods for controlling dynamic systems |
| 08/24/2006 | WO2006065895A3 System and method for import and export from a solid modeling program |
| 08/24/2006 | WO2006060105A9 Systems and methods for benchmarking performance data |
| 08/24/2006 | WO2006047542A3 System and method for robotic assisted wig construction |
| 08/24/2006 | WO2006037613A3 Method and system for implementing an enhanced database |
| 08/24/2006 | WO2006034352A3 Automatic generation of code for component interfaces in models |
| 08/24/2006 | WO2006017453A3 Method apparatus and system for visualization of probabilistic models |
| 08/24/2006 | WO2005114468A3 System and method for text segmentation and display |
| 08/24/2006 | WO2005114467A3 Computer-based system and computer program product for collaborative editing of documents |
| 08/24/2006 | WO2005103878A3 Method and system for compression of files for storage and operation on compressed files |
| 08/24/2006 | WO2005100101A3 Method and device for analyzing and evaluating a signal, especially a sensor signal |
| 08/24/2006 | WO2005093600A3 Induction of grammar rules |
| 08/24/2006 | WO2005084354A3 Method of attaching an rf id tag to a hose and tracking system |
| 08/24/2006 | WO2005081637A3 Interactive system for building, organising, and sharing one’s own databank of works of literature in one or more languages |
| 08/24/2006 | WO2005072351A3 Rule selection engine |
| 08/24/2006 | WO2005069127A3 Method for automatic recovery of uml model requirements and updating thereof |
| 08/24/2006 | WO2005053323A3 Groupware systems and methods |
| 08/24/2006 | WO2005050367A3 Systems and methods for search query processing using trend analysis |
| 08/24/2006 | WO2005048309A3 Delta-geometry timing prediction in integrated circuit fabrication |
| 08/24/2006 | WO2005041895A8 Albumin binding sites for evaluating drug interactions and methods of evaluating or designing drugs based on their albumin binding properties |
| 08/24/2006 | WO2005038614A3 System and method for facilitating asynchronous disconnected operations for data access over a network |
| 08/24/2006 | WO2005038575A3 Serving content-targeted ads in e-mail, such as e-mail newsletters |
| 08/24/2006 | WO2005025115A8 Relationship user interface |
| 08/24/2006 | WO2005012951A3 Three-dimensional simultaneous multiple-surface method and free-form illumination-optics designed therefrom |
| 08/24/2006 | US20060191022 Method and apparatus for article authentication |
| 08/24/2006 | US20060191020 Peer-to-peer network communication |
| 08/24/2006 | US20060191016 Systems and methods for free demonstration of online premium content prior to purchase |
| 08/24/2006 | US20060191013 Offering different product costs options based on privacy policy acceptance |
| 08/24/2006 | US20060191002 Packet security method and apparatus |
| 08/24/2006 | US20060191000 Key distribution and caching mechanism to facilitate client handoffs in wireless network systems |
| 08/24/2006 | US20060190983 Disk driver cluster management of time shift buffer with file allocation table structure |
| 08/24/2006 | US20060190982 Method for identifying extender text table of electronic program guide in digital TV |
| 08/24/2006 | US20060190966 Systems and methods for providing a program as a gift using an interactive application |
| 08/24/2006 | US20060190921 Manufacturing Method of Semiconductor Device |
| 08/24/2006 | US20060190920 Optical proximity correction performed with respect to limited area |
| 08/24/2006 | US20060190919 Method of locating sub-resolution assist feature(s) |
| 08/24/2006 | US20060190918 System and process for manufacturing custom electronics by combining traditional electronics with printable electronics |
| 08/24/2006 | US20060190917 System and process for manufacturing application specific printable circuits (ASPC'S) and other custom electronic devices |
| 08/24/2006 | US20060190916 Semiconductor substrate processing method and apparatus |
| 08/24/2006 | US20060190915 Machine specific and machine group correction of masks based on machine subsystem performance parameters |
| 08/24/2006 | US20060190914 Method and apparatus for identifying a problem edge in a mask layout using an edge-detecting process-sensitivity model |
| 08/24/2006 | US20060190913 Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model |
| 08/24/2006 | US20060190912 Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model |
| 08/24/2006 | US20060190911 Translation generation for a mask pattern |
| 08/24/2006 | US20060190910 Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs |
| 08/24/2006 | US20060190909 Method for designing a system LSI |
| 08/24/2006 | US20060190908 Coding of FPGA and standard cell logic in a tiling structure |
| 08/24/2006 | US20060190907 Methods and apparatus for implementing parameterizable processors and peripherals |
| 08/24/2006 | US20060190906 Efficient method for mapping a logic design on field programmable gate arrays |
| 08/24/2006 | US20060190905 System for designing re-programmable digital hardware platforms |
| 08/24/2006 | US20060190904 Common interface framework for developing field programmable device based applications independent of a target circuit board |
| 08/24/2006 | US20060190903 ASICs having programmable bypass of design faults |
| 08/24/2006 | US20060190902 Method, apparatus and program for automatically routing semiconductor integrated circuit |
| 08/24/2006 | US20060190901 Method of buffer insertion to achieve pin specific delays |
| 08/24/2006 | US20060190900 Method, system and computer program product for automatically estimating pin locations and interconnect parasitics of a circuit layout |
| 08/24/2006 | US20060190899 Method of clock tree distribution generation by determining allowed placement regions for clocked elements |
| 08/24/2006 | US20060190898 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing |
| 08/24/2006 | US20060190897 Methods of routing an integrated circuit design |
| 08/24/2006 | US20060190896 Method for reducing the size and nanowire length used in nanowire crossbars without reducing the number of nanowire junctions |
| 08/24/2006 | US20060190895 Method and program for designing semiconductor device |
| 08/24/2006 | US20060190894 Area-efficient distributed device structure for integrated voltage regulators |
| 08/24/2006 | US20060190893 Logic cell layout architecture with shared boundary |
| 08/24/2006 | US20060190892 System and method for automatic insertion of on-chip decoupling capacitors |
| 08/24/2006 | US20060190891 Method for placing probing pad and computer readable recording medium for storing program thereof |
| 08/24/2006 | US20060190890 Cell instance generating method |
| 08/24/2006 | US20060190889 Circuit floorplanning and placement by look-ahead enabled recursive partitioning |
| 08/24/2006 | US20060190888 Apparatus and method for electronic device design |
| 08/24/2006 | US20060190887 Method for realizing circuit layout |
| 08/24/2006 | US20060190886 Optimizing IC clock structures by minimizing clock uncertainty |
| 08/24/2006 | US20060190885 Method of displaying delay |
| 08/24/2006 | US20060190884 Apparatus and method for analyzing post-layout timing critical paths |
| 08/24/2006 | US20060190883 System and method for unfolding/replicating logic paths to facilitate propagation delay modeling |
| 08/24/2006 | US20060190882 System and method for generating assertions using waveforms |
| 08/24/2006 | US20060190881 Method for estimating propagation noise based on effective capacitance in an integrated circuit chip |
| 08/24/2006 | US20060190880 Output buffer with slew rate control utilizing an inverse process dependent current reference |
| 08/24/2006 | US20060190879 Frequency dependent timing margin |
| 08/24/2006 | US20060190878 Method and circuit arrangement for determining power supply noise |
| 08/24/2006 | US20060190877 Decoupling capacitance analysis method |
| 08/24/2006 | US20060190876 Semiconductor device design system and method, and software product for the same |
| 08/24/2006 | US20060190875 Pattern extracting system, method for extracting measuring points, method for extracting patterns, and computer program product for extracting patterns |
| 08/24/2006 | US20060190874 Method and system for formal unidirectional bus verification |
| 08/24/2006 | US20060190873 Exploiting suspected redundancy for enhanced design verification |
| 08/24/2006 | US20060190872 System and method for signal integrity testing of electronic circuits |
| 08/24/2006 | US20060190871 Methods, systems and media for managing functional verification of a parameterizable design |
| 08/24/2006 | US20060190870 Latch modeling technique for formal verification |
| 08/24/2006 | US20060190869 Design verification using sequential and combinational transformations |
| 08/24/2006 | US20060190868 Method and system for optimized handling of constraints during symbolic simulation |
| 08/24/2006 | US20060190867 Method for reconfiguration of random biases in a synthesized design without recompilation |
| 08/24/2006 | US20060190866 Resistance extraction for hierarchical circuit artwork |
| 08/24/2006 | US20060190865 Quantified boolean formula (QBF) solver |
| 08/24/2006 | US20060190864 Efficient modeling of embedded memories in bounded memory checking |
| 08/24/2006 | US20060190863 Method for improving accuracy of MOSFET models used in circuit simulation integrated circuits |
| 08/24/2006 | US20060190862 Event driven switch level simulation method and simulator |
| 08/24/2006 | US20060190861 Method and apparatus for evaluating coverage of circuit, and computer product |
| 08/24/2006 | US20060190860 Method and system for debugging using replicated logic and trigger logic |