Patents
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
05/1997
05/27/1997US5634122 System and method for multi-level token management for distributed file systems
05/27/1997US5634117 Apparatus for operating a microprocessor core and bus controller at a speed greater than the speed of a bus clock speed
05/27/1997US5634112 Memory controller having precharge prediction based on processor and PCI bus cycles
05/27/1997US5634111 Computer system including a device with a plurality of identifiers
05/27/1997US5634099 Direct memory access unit for transferring data between processor memories in multiprocessing systems
05/27/1997US5634081 System for starting and completing a data transfer for a subsequently received autotransfer command after receiving a first SCSI data transfer command that is not autotransfer
05/27/1997US5634080 Hand-held portable computer having an electroluminescent flat-panel display with pixel elements at right angles to the plane of the display and an excitation direction parallel to the plane of the display
05/27/1997US5634077 Information processing system with control methods and apparatus for information storage and interrupt request handling scheme
05/27/1997US5634076 Digital signal processor
05/27/1997US5634074 Serial I/O device identifies itself to a computer through a serial interface during power on reset then it is being configured by the computer
05/27/1997US5634073 System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation
05/27/1997US5634069 Encoding assertion and de-assertion of interrupt requests and DMA requests in a serial bus I/O system
05/27/1997US5634060 Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus
05/27/1997US5634057 In a computer system
05/27/1997US5634045 Integrated circuit input/output processor having improved timer capability
05/27/1997US5634042 Data transfer apparatus that compensates for differential signal delays
05/27/1997US5634037 Multiprocessor system having a shared memory with exclusive access for a requesting processor which is maintained until normal completion of a process and for retrying the process when not normally completed
05/27/1997US5634035 In a data transmission system
05/27/1997US5634034 Enhanced processor buffered interface for multiprocess systems
05/27/1997US5634029 Apparatus for interchanging floppy diskette drive assignments
05/27/1997US5634015 Generic high bandwidth adapter providing data communications between diverse communication networks and computer system
05/27/1997US5634014 Semiconductor process, power supply voltage and temperature compensated integrated system bus termination
05/27/1997US5634013 In a computer bus bridge
05/27/1997US5634007 Independent computer storage addressing in input/output transfers
05/27/1997US5634006 System and method for ensuring QOS in a token ring network utilizing an access regulator at each node for allocating frame size for plural transmitting applications based upon negotiated information and priority in the network
05/27/1997US5633992 Low-level direct connect for PCL printers
05/27/1997US5633919 Real-time billing system for a call processing system
05/27/1997US5633890 Method for intelligent data terminal equipment (DTE) data communication
05/27/1997US5633870 Method and apparatus for controlling data flow through an ATM interface
05/27/1997US5633810 Video server system
05/27/1997US5633605 Dynamic bus with singular central precharge
05/27/1997US5632681 Universal electronic video game renting/distributing system
05/25/1997CA2190910A1 Network communications subsystem for networked digital computer system
05/22/1997WO1997018665A1 Internet global area networks fax system
05/22/1997WO1997018635A2 Multiprotocol communication between a generic web browser and several access servers
05/22/1997WO1997018604A1 Computer system backplane having ground tabs for interconnecting the backplane ground to the computer system chassis
05/22/1997WO1997018602A1 A dual-in-line universal serial bus connector
05/22/1997DE19648078A1 Program interrupter generation device e.g. for microcomputer
05/22/1997DE19648065A1 Data store control device e.g. for digital printing and copying machines
05/22/1997DE19629188A1 Clock and combined clock and message routing signal transmission system
05/22/1997CA2237596A1 Architecture for processing bit-map data for a raster printer
05/22/1997CA2237328A1 Computer system backplane having ground tabs for interconnecting the backplane ground to the computer system chassis
05/22/1997CA2235501A1 Information handling system for allowing a generic web browser to access servers of a plurality of different protocol types
05/21/1997EP0774878A2 Resource management system for a broadband multipoint bridge
05/21/1997EP0774877A2 ISDN terminal with activatable/deactivatable extension of the command set
05/21/1997EP0774853A2 Method and system for graphically displaying and navigating through an interactive voice response menu
05/21/1997EP0774723A2 Virtual file management system
05/21/1997EP0774719A1 A multimedia based reporting system with recording and playback of dynamic annotation
05/21/1997EP0774717A1 Apparatus and method for providing a generic interface between a host system and an asynchronous transfer mode core functional block
05/21/1997EP0774713A1 Integrated circuit with programmable bus configuration
05/21/1997EP0774137A1 Dynamic device matching using driver candidate lists
05/21/1997CN2254568Y Microcomputer interface sharing device
05/21/1997CN1150488A Trainable user interface translator
05/21/1997CN1150375A Method of controlling exchange, and exchange and communications system
05/21/1997CN1150278A Method and system for archiving information on communication network
05/20/1997US5632029 Multi-segmented bus and method of operation
05/20/1997US5632021 Computer system with cascaded peripheral component interconnect (PCI) buses
05/20/1997US5632020 System for docking a portable computer to a host computer without suspending processor operation by a docking agent driving the bus inactive during docking
05/20/1997US5632018 Electronic mail system
05/20/1997US5632016 In a computer system
05/20/1997US5631897 Apparatus and method for incorporating a large number of destinations over circuit-switched wide area network connections
05/20/1997US5631701 Image data transfer system operable with an electronic still camera
05/20/1997US5631651 Telecom adapter for interfacing computing devices to the analog telephone network
05/20/1997US5631637 Output method for dot data and apparatus therefor
05/20/1997US5630757 Real-time multi-user game communication system using existing cable television infrastructure
05/20/1997CA2084376C Common file access system and a common file access method in a distributed memory type computer system
05/20/1997CA2071709C System for automatically generating and saving control information in a server if requested by a client at system initialization for operating in a network
05/20/1997CA2048488C Telecomputer package switching system
05/18/1997CA2186795A1 Resource management system for a broadband multipoint bridge
05/15/1997WO1997017678A1 A system, a method and an apparatus for performing an electric payment transaction in a telecommunication metwork
05/15/1997WO1997017667A1 Enhanced detection of multiple data transmissions
05/15/1997WO1997017662A1 Method and apparatus for server-independent caching of dynamically-generated customized pages
05/15/1997DE19541946A1 Memory access control for thirty-two bit high power third generation microprocessor e.g. Motorola MC 68040 (RTM)
05/15/1997DE19526802C1 Arrangement for controlling bidirectional, asynchronous and serial transfer of data packets
05/15/1997DE19526799C1 Arrangement for parallel data communications between data processor and bus controller
05/15/1997DE19526798C1 Arrangement for controlling bidirectional, asynchronous and serial transfer of data packets
05/14/1997EP0773698A2 Method for logical network design in multi-service networks
05/14/1997EP0773649A2 Network topology management system
05/14/1997EP0773500A1 Dual mode arbitration method for computer systems with zero to two cycles of latency
05/14/1997EP0773491A2 Integrated circuit input/output processor having improved timer capability
05/14/1997EP0772942A1 Apparatus for managing a telecommunications network
05/14/1997EP0772833A1 Serial interface capable of operating in two different serial data transfer modes
05/14/1997EP0772832A1 Arbitration in case of a retarding bus coupling
05/14/1997EP0772831A1 Bidirectional parallel signal interface
05/14/1997EP0772830A1 Data reduction for bus couplers
05/14/1997EP0772825A1 Computer system having client-server architecture
05/14/1997EP0733233A4 Apparatus and method for signal processing
05/14/1997EP0651920A4 Apparatus for connecting computer devices.
05/14/1997CN1149805A Multipoint broadcast step speed control in image serivce device environment
05/14/1997CN1149804A Method and device for providing interactive guide on information net for gaining affairs
05/14/1997CN1149797A Relicable control and access method and system for system resource in distribating system
05/13/1997US5630184 Method of operating a computer forming a node in a network
05/13/1997US5630174 For use within a computer system
05/13/1997US5630173 In a computer system
05/13/1997US5630172 Data transfer control apparatus wherein an externally set value is compared to a transfer count with a comparison of the count values causing a transfer of bus use right
05/13/1997US5630171 Translating from a PIO protocol to DMA protocol with a peripheral interface circuit
05/13/1997US5630169 Apparatus for a host central processor with associated controller to capture a selected one of a number of memory units via path control commands
05/13/1997US5630167 Electronic apparatus having a plurality of connectors each connecting one of a plurality of kinds of cards
05/13/1997US5630163 Computer having a single bus supporting multiple bus architectures operating with different bus parameters
05/13/1997US5630152 Communication protocol between master and slave device with register information sharing