Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
07/2013
07/02/2013US8478834 Low latency, high bandwidth data communications between compute nodes in a parallel computer
07/02/2013US8478577 Modeling of a multiprocessor system
07/02/2013US8477946 Method and apparatus for protecting encryption keys in a logically partitioned computer system environment
07/02/2013US8477544 Circuit apparatus and system
07/02/2013US8477358 Printer, terminal, and printing system with operating state communication
07/02/2013US8475251 Systems and methods for coding competitions
07/02/2013US8474628 Presenting a recipient of an e-mail with an option to instant message a sender or another recipient based on the sender's or the other recipient's address and online status
07/02/2013CA2601730C System and method for efficient transfer of applications and data during device swap
07/02/2013CA2500894C Efficient algorithm and protocol for remote differential compression
07/02/2013CA2463671C A system and method to display and navigate large images
06/2013
06/27/2013WO2013096510A1 Storing data using a direct data path architecture to reduce energy consumption and improve performance
06/27/2013WO2013096490A2 Data bus inversion coding
06/27/2013WO2013095944A1 An asymmetric performance multicore architecture with same instruction set architecture (isa)
06/27/2013WO2013095943A1 System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time
06/27/2013WO2013095933A1 A method, apparatus, and system for energy efficiency and energy conservation including enhanced temperature based voltage control
06/27/2013WO2013095820A1 A method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply
06/27/2013WO2013095814A1 A method, apparatus, and system for energy efficiency and energy conservation through dynamic management of memory and input/output subsystems
06/27/2013WO2013095777A1 Safely ejecting a client device using a dedicated button
06/27/2013WO2013095665A1 Tracking distributed execution on on-chip multinode networks without a centralized mechanism
06/27/2013WO2013095654A1 Shared send queue
06/27/2013WO2013095641A1 Sub-block based wear leveling
06/27/2013WO2013095640A1 Methods and apparatus for efficient communication between caches in hierarchical caching design
06/27/2013WO2013095639A1 Utility and lifetime based cache replacement policy
06/27/2013WO2013095580A1 Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
06/27/2013WO2013095571A1 Method and apparatus to tunnel messages to storage devices by overloading read/write commands
06/27/2013WO2013095567A1 Non-linear termination for an on-package input/output architecture
06/27/2013WO2013095566A1 Systems and methods for providing dynamic file system awareness on storage devices
06/27/2013WO2013095564A1 Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride
06/27/2013WO2013095563A1 Packed data rearrangement control indexes precursors generation processors, methods, systems, and instructions
06/27/2013WO2013095562A1 Method, device and system for aggregation of shared address devices
06/27/2013WO2013095561A1 Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces
06/27/2013WO2013095560A1 Sideband initialization
06/27/2013WO2013095558A1 Method, apparatus and system for execution of a vector calculation instruction
06/27/2013WO2013095557A1 Deterministic clock crossing
06/27/2013WO2013095555A1 Packed data rearrangement control indexes generation processors, methods, systems, and instructions
06/27/2013WO2013095551A1 Mechanisms for clock gating
06/27/2013WO2013095549A1 Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces
06/27/2013WO2013095545A1 Distributed electrostatic discharge protection for an on-package input/output architecture
06/27/2013WO2013095538A1 Interconnection of multiple chips in a package utilizing on-package input/output interfaces
06/27/2013WO2013095537A1 Controlling a processor cache using a real-time attribute
06/27/2013WO2013095536A1 On-package input/output architecture
06/27/2013WO2013095535A1 Floating point rounding processors, methods, systems, and instructions
06/27/2013WO2013095533A1 Fault-aware mapping for shared last level cache (llc)
06/27/2013WO2013095530A1 Efficient pcms refresh mechanism background
06/27/2013WO2013095529A1 Addition instructions with independent carry chains
06/27/2013WO2013095520A1 Object-aware storage
06/27/2013WO2013095519A1 Method and apparatus for clock frequency ratio independent error logging
06/27/2013WO2013095518A1 Accessing data stored in a command/address register device
06/27/2013WO2013095510A1 Packed data operation mask concatenation processors, methods, systems, and instructions
06/27/2013WO2013095508A1 Speculative cache modification
06/27/2013WO2013095493A1 Instructions to perform groestl hashing
06/27/2013WO2013095475A1 Apparatus and method for memory-hierarchy aware producer-consumer instruction
06/27/2013WO2013095471A1 Method and apparatus for a partial-address select-signal generator with address shift
06/27/2013WO2013095469A1 Psmi using at-speed scan capture
06/27/2013WO2013095465A1 High-performance storage structures and systems featuring multiple non-volatile memories
06/27/2013WO2013095464A1 Apparatus and method for memory-hierarchy aware producer-consumer instruction
06/27/2013WO2013095456A1 Power management in a discrete memory portion
06/27/2013WO2013095448A1 Dram compression scheme to reduce power consumption in motion compensation and display refresh
06/27/2013WO2013095436A1 Method and apparatus for setting an i/o bandwidth-based processor frequency floor
06/27/2013WO2013095422A1 Dynamic link width adjustment
06/27/2013WO2013095411A1 INCORPORATING ACCESS CONTROL FUNCTIONALITY INTO A SYSTEM ON A CHIP (SoC)
06/27/2013WO2013095409A1 Near field communications-triggering for wireless display/docking
06/27/2013WO2013095388A1 Protocol for conflicting memory transactions
06/27/2013WO2013095387A1 Secure replay protected storage
06/27/2013WO2013095381A1 Method and system for data de-duplication
06/27/2013WO2013095338A1 Simd integer multiply-accumulate instruction for multi-precision arithmetic
06/27/2013WO2013095257A1 Digital signal processor and method for addressing a memory in a digital signal processor
06/27/2013WO2013095133A1 Lighting system and method of retrieving status information of a lighting system
06/27/2013WO2013094751A1 Set-up system, method and computer program for application software
06/27/2013WO2013094353A1 Information-sharing device, information-sharing method, information-sharing program and terminal device
06/27/2013WO2013094280A1 Storage device access system
06/27/2013WO2013094157A1 Cache device, communication method, and program
06/27/2013WO2013094137A1 Communication system, transcoder, communication method, and program
06/27/2013WO2013094047A1 Management device, management program, and management method
06/27/2013WO2013094031A1 Information processor and recording apparatus using same
06/27/2013WO2013094020A1 Electronic apparatus, control method, program, and recording medium
06/27/2013WO2013094010A1 Data transferring apparatus, data transferring method, and inter-chip communication system
06/27/2013WO2013094007A1 Load distribution system
06/27/2013WO2013093994A1 Storage system, data rebalancing program and data rebalancing method
06/27/2013WO2013093970A1 Digital signage system and terminal device
06/27/2013WO2013093702A1 Network device configuration management
06/27/2013WO2013093336A1 Method for communicating between at least one first system and at least one second system
06/27/2013WO2013092419A1 System and method for communication between a data-acquisition circuit and a data-processing circuit
06/27/2013WO2013092101A1 Synchronous data transmission device
06/27/2013WO2013091928A1 Data exchange and storage device
06/27/2013WO2013030674A3 System and methods for generating and managing a virtual device
06/27/2013WO2012057767A8 Land grid array socket assembly
06/27/2013US20130167226 Handheld Mobile Device with USB Hard Drive and Optional Biometric Scanner, and Systems Including the Same
06/27/2013US20130167160 Abstracting Data Acquisition And Management
06/27/2013US20130167028 Restricting media content rendering
06/27/2013US20130166866 Systems and methods of performing a data save operation
06/27/2013US20130166813 Multi-protocol i/o interconnect flow control
06/27/2013US20130166812 Transport of pci-ordered traffic over independent networks
06/27/2013US20130166811 Methods and structure for communicating between a sata host and a sata target device through a sas domain
06/27/2013US20130166810 Apparatus for processing register window overflow and underflow
06/27/2013US20130166809 Drive circuit for peripheral component interconnect-express (pcie) slots
06/27/2013US20130166808 Docking station for electronic device
06/27/2013US20130166807 Safely ejecting a client device using a dedicated button
06/27/2013US20130166806 Pci riser card
06/27/2013US20130166805 Interrupt cause management device and interrupt processing system
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