Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
09/2014
09/18/2014US20140281582 Protecting visible data during computerized process usage
09/18/2014US20140281576 Information providing system, information processing apparatus, computer readable medium, and information providing method
09/18/2014US20140281513 Block encryption
09/18/2014US20140281499 Method and system for enabling communications between unrelated applications
09/18/2014US20140281467 System and method for execution of a secured environment initialization instruction
09/18/2014US20140281367 Address calculation for received data
09/18/2014US20140281366 Address translation in a system using memory striping
09/18/2014US20140281365 Frame buffer access tracking via a sliding window in a unified virtual memory system
09/18/2014US20140281364 Microcontroller for memory management unit
09/18/2014US20140281363 Multi-threaded memory management
09/18/2014US20140281362 Memory allocation in a system using memory striping
09/18/2014US20140281361 Nonvolatile memory device and related deduplication method
09/18/2014US20140281360 Apparatus and method for insertion and deletion in multi-dimensional to linear address space translation
09/18/2014US20140281359 Apparatus and method for referencing dense and sparse information in multi-dimensional to linear address space translation
09/18/2014US20140281358 Migration scheme for unified virtual memory system
09/18/2014US20140281357 Common pointers in unified virtual memory system
09/18/2014US20140281356 Microcontroller for memory management unit
09/18/2014US20140281355 Virtual storage pool
09/18/2014US20140281354 Continuous run-time integrity checking for virtual memory
09/18/2014US20140281353 Hardware-based pre-page walk virtual address transformation
09/18/2014US20140281352 Mechanism for facilitating dynamic and efficient management of translation buffer prefetching in software programs at computing systems
09/18/2014US20140281351 Stride-based translation lookaside buffer (tlb) prefetching with adaptive offset
09/18/2014US20140281349 Receive-side scaling in a computer system
09/18/2014US20140281348 Managing cpu resources for high availability micro-partitions
09/18/2014US20140281347 Managing cpu resources for high availability micro-partitions
09/18/2014US20140281346 Managing cpu resources for high availability micro-partitions
09/18/2014US20140281345 Distributed Storage Allocation for Heterogeneous Systems
09/18/2014US20140281344 Data processing system and method of operating the same
09/18/2014US20140281343 Information processing apparatus, program, and memory area allocation method
09/18/2014US20140281342 Migrating and retrieving queued data in byte-addressable storage
09/18/2014US20140281340 Multidimensional resource manager/allocator
09/18/2014US20140281338 Host-driven garbage collection
09/18/2014US20140281337 Storage system, storage apparatus, and computer product
09/18/2014US20140281336 Memory allocation accelerator
09/18/2014US20140281334 Address Resource Mapping In A Shared Memory Computer System
09/18/2014US20140281333 Paging enablement for data storage
09/18/2014US20140281332 Externally programmable memory management unit
09/18/2014US20140281331 Systems and methods for processing data stored in data storage devices
09/18/2014US20140281330 Apparatus and Method for Resource Alerts
09/18/2014US20140281323 Migration directives in a unified virtual memory system architecture
09/18/2014US20140281321 Register access white listing
09/18/2014US20140281320 Forensic Computer Examination Systems and Methods
09/18/2014US20140281318 Efficiently searching and modifying a variable length queue
09/18/2014US20140281312 Apparatus and method for translation from multi-dimensional to linear address space in storage
09/18/2014US20140281299 Opportunistic migration of memory pages in a unified virtual memory system
09/18/2014US20140281298 Method and Appartus for Suggesting Data for Deletion
09/18/2014US20140281297 Migration of peer-mapped memory pages
09/18/2014US20140281296 Fault buffer for tracking page faults in unified virtual memory system
09/18/2014US20140281295 Expediting RCU Grace Periods Under User Mode Control
09/18/2014US20140281293 Method of operating memory controller and devices including memory controller
09/18/2014US20140281292 Remote enabling of storage
09/18/2014US20140281291 Method and Apparatus for Memory Array Access
09/18/2014US20140281290 Dynamic definition of error information in a programmable device
09/18/2014US20140281286 Memory system
09/18/2014US20140281281 Host command based read disturb methodology
09/18/2014US20140281277 Integrated system and storage media controlller
09/18/2014US20140281276 Method, apparatus, and system for low latency communication
09/18/2014US20140281275 Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system
09/18/2014US20140281274 Shared memory interleavings for instruction atomicity violations
09/18/2014US20140281273 Providing Local Cache Coherency in a Shared Storage Environment
09/18/2014US20140281272 Rapid Recovery From Downtime Of Mirrored Storage Device
09/18/2014US20140281271 Cache control device, processor, information processing system, and cache control method
09/18/2014US20140281270 Mechanism to improve input/output write bandwidth in scalable systems utilizing directory based coherecy
09/18/2014US20140281268 Enabling Hardware Transactional Memory To Work More Efficiently With Readers That Can Tolerate Stale Data
09/18/2014US20140281267 Enabling Hardware Transactional Memory To Work More Efficiently With Readers That Can Tolerate Stale Data
09/18/2014US20140281266 Maintaining Coherence When Removing Nodes From a Directory-Based Shared Memory System
09/18/2014US20140281265 Write admittance policy for a memory cache
09/18/2014US20140281264 Migration counters for hybrid memories in a unified virtual memory system
09/18/2014US20140281263 Replaying memory transactions while resolving memory access faults
09/18/2014US20140281262 Dynamic caching module selection for optimized data deduplication
09/18/2014US20140281261 Increased error correction for cache memories through adaptive replacement policies
09/18/2014US20140281260 Estimating access frequency statistics for storage device
09/18/2014US20140281259 Translation lookaside buffer entry systems and methods
09/18/2014US20140281258 Dynamic caching module selection for optimized data deduplication
09/18/2014US20140281257 Caching Backed-Up Data Locally Until Successful Replication
09/18/2014US20140281256 Fault buffer for resolving page faults in unified virtual memory system
09/18/2014US20140281255 Page state directory for managing unified virtual memory
09/18/2014US20140281254 Semiconductor Chip With Adaptive BIST Cache Testing During Runtime
09/18/2014US20140281253 Dynamically removing entries from an executing queue
09/18/2014US20140281252 Statement cache auto-tuning
09/18/2014US20140281251 Method and apparatus for cache line state update in sectored cache with line state tracker
09/18/2014US20140281250 Systems and Methods for Performing Data Recovery in a Memory System
09/18/2014US20140281249 Hash-based spatial sampling for efficient cache utility curve estimation and cache allocation
09/18/2014US20140281248 Read-write partitioning of cache memory
09/18/2014US20140281247 Method to accelerate queries using dynamically generated alternate data formats in flash cache
09/18/2014US20140281246 Instruction boundary prediction for variable length instruction set
09/18/2014US20140281245 Virtual unified instruction and data caches
09/18/2014US20140281244 Storage apparatus and control method for storage apparatus
09/18/2014US20140281243 Multiple-core computer processor
09/18/2014US20140281242 Methods, systems and apparatus for predicting the way of a set associative cache
09/18/2014US20140281241 Cached evaluation of paths through graph-based data representation
09/18/2014US20140281240 Instructions To Mark Beginning and End Of Non Transactional Code Region Requiring Write Back To Persistent Storage
09/18/2014US20140281239 Adaptive hierarchical cache policy in a microprocessor
09/18/2014US20140281238 Systems and methods for accessing cache memory
09/18/2014US20140281237 Broadcast cache coherence on partially-ordered network
09/18/2014US20140281236 Systems and methods for implementing transactional memory
09/18/2014US20140281235 System and Method for Software/Hardware Coordinated Adaptive Performance Monitoring
09/18/2014US20140281234 Serving memory requests in cache coherent heterogeneous systems
09/18/2014US20140281232 System and Method for Capturing Behaviour Information from a Program and Inserting Software Prefetch Instructions
09/18/2014US20140281231 Electronic device and method for fabricating the same
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