Patents
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
07/2001
07/18/2001EP0839421A4 Allocated and dynamic switch flow control
07/18/2001EP0839420A4 Allocated and dynamic bandwidth management
07/18/2001CN1304610A Method and apparatus for secure data transmission system
07/18/2001CN1304604A Multi-node encryption and key delivery
07/18/2001CN1304508A Method and apparatus for secure address re-mapping
07/18/2001CN1304507A File managing system, file managing device, film managing method, and program recording medium
07/18/2001CN1304503A Integration of security modules on integrated circuit
07/18/2001CN1304116A Equipment of data processing and method operating said equipment
07/18/2001CN1304112A System for electronized data administration and its method
07/18/2001CN1304105A Portable terminal, servecx, system and their program recording medium
07/18/2001CN1304102A Universal computer and administration method of copyright using therein
07/18/2001CN1304096A Quick scrambler and encryption method
07/18/2001CN1068687C Dynamic allocation method for storage with multi-stage voice
07/17/2001US6263445 Method and apparatus for authenticating connections to a storage system coupled to a network
07/17/2001US6263422 Pipeline processing machine with interactive stages operable in response to tokens and system and methods relating thereto
07/17/2001US6263421 Virtual memory system that is portable between different CPU types
07/17/2001US6263414 Memory for accomplishing lowered granularity of a distributed shared memory
07/17/2001US6263413 Memory integrated circuit and main memory and graphics memory systems applying the above
07/17/2001US6263410 Apparatus and method for asynchronous dual port FIFO
07/17/2001US6263408 Method and apparatus for implementing automatic cache variable update
07/17/2001US6263407 Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode
07/17/2001US6263406 Parallel processor synchronization and coherency control method and system
07/17/2001US6263405 Multiprocessor system
07/17/2001US6263404 Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system
07/17/2001US6263403 Method and apparatus for linking translation lookaside buffer purge operations to cache coherency transactions
07/17/2001US6263402 Data caching on the internet
07/17/2001US6263398 Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache
07/17/2001US6263379 Method and system for referring to and binding to objects using identifier objects
07/17/2001US6263360 System uses filter tree and feed handler for updating objects in a client from a server object list
07/17/2001US6263350 Method and system for leasing storage
07/17/2001US6263347 System for linking data between computer and portable remote terminal and data linking method therefor
07/17/2001US6263341 Information repository system and method including data objects and a relationship object
07/17/2001US6263338 Method relating to databases
07/17/2001US6262940 Semiconductor memory device and method for improving the transmission data rate of a data input and output bus and memory module
07/17/2001US6262926 Nonvolatile semiconductor memory device
07/17/2001US6262918 Space management for managing high capacity nonvolatile memory
07/17/2001US6262751 Hardware rotation of an image on a computer display
07/14/2001CA2328044A1 Method and apparatus for transferring data files retrievable via a communications network
07/12/2001WO2001050752A1 Ratings control system with temporary override capability and store-recall feature
07/12/2001WO2001050751A1 Ratings control system with temporary override capability and conflict resolution feature
07/12/2001WO2001050530A1 Anti tamper encapsulation for an integrated circuit
07/12/2001WO2001050474A1 Method and apparatus for exercising external memory with a memory built-in self-test
07/12/2001WO2001050422A1 A system and method for the construction of data
07/12/2001WO2001050275A1 A method for employing a page prefetch cache for database applications
07/12/2001WO2001050274A1 Cache line flush micro-architectural implementation method and system
07/12/2001WO2001050273A1 Set-associative cache-management method using parallel reads and serial reads initiated while processor is waited
07/12/2001WO2001050272A1 Cache which provides partial tags from non-predicted ways to direct search if way prediction misses
07/12/2001WO2001050270A2 Methods and apparatus for improving locality of reference through memory management
07/12/2001WO2001050269A2 A method and apparatus to perform a round robin and locking cache replacement scheme
07/12/2001WO2001050267A2 Dual cache with multiple interconnection operation
07/12/2001WO2001050254A1 Method and system for an inuse field resource management scheme
07/12/2001WO2001050228A2 Low latency multi-level communication interface
07/12/2001WO2001005158A9 Methods and apparatus for selecting multicast ip data transmitted in broadcast streams
07/12/2001US20010008018 Disk system and power-on sequence for the same
07/12/2001US20010008016 Information management method and information management apparatus
07/12/2001US20010008014 Automatic network connection using a smart card
07/12/2001US20010008010 Fiber channel connection storage controller
07/12/2001US20010008009 Set-associative cache-management method with parallel and single-set sequential reads
07/12/2001US20010008008 Information recording apparatus and control method thereof
07/12/2001US20010008002 Image processing apparatus and method
07/12/2001US20010007986 Database processing method
07/12/2001US20010007538 Single-Port multi-bank memory system having read and write buffers and method of operating same
07/12/2001DE19964012A1 Refreshing memory contents of read only memory cell involves comparing current memory cell charge state with threshold value above reading charge, raising charge state if below threshold
07/12/2001DE19963689A1 Schaltungsanordnung eines integrierten Halbleiterspeichers zum Speichern von Adressen fehlerhafter Speicherzellen Circuit arrangement of an integrated semiconductor memory for storing addresses of defective memory cells
07/12/2001DE19963208A1 Manipulation detection of programmable memory device in digital controller involves checking information about programming/reprogramming process stored in separate memory area
07/12/2001DE10000503A1 Datenverarbeitungseinrichtung und Verfahren zu dessen Betrieb Data processing device and method for its operation
07/12/2001CA2396768A1 Methods and apparatus for improving locality of reference through memory management
07/12/2001CA2395656A1 Anti tamper encapsulation for an integrated circuit
07/12/2001CA2395647A1 A system and method for the construction of data
07/12/2001CA2394207A1 Ratings control system with temporary override capability and store-recall feature
07/12/2001CA2394206A1 Ratings control system with temporary override capability and conflict resolution feature
07/11/2001EP1115207A1 Method of generating distribution content, method and apparatus for content distribution, and method of code conversion
07/11/2001EP1115094A2 Data processing device and its method of operation
07/11/2001EP1115078A2 Electronic data management system and method
07/11/2001EP1115063A1 Non-volatile semiconductor memory device with error management
07/11/2001EP1115050A2 General purpose computer and copyright management method for use therein
07/11/2001EP1114544A1 Method for distributing the load of a communication channel
07/11/2001EP1114375A1 Database synchronization and organization system and method
07/11/2001EP1114367A1 Method and apparatus for accessing a complex vector located in a dsp memory
07/11/2001EP1012721B1 Data file storage management system for snapshot copy operations
07/11/2001EP0673529B1 A method for relations recovery of a data base in case of errors
07/11/2001CN1303498A Method for accessing individually addressable and data processing system
07/11/2001CN1303065A Data bank management device and encryption/deciphering system
07/11/2001CN1303059A Geographical information display device and method
07/11/2001CN1303053A Queue supervisor of buffer
07/11/2001CN1303050A Dynamic random access memory data storage and movement for network processor
07/11/2001CN1303044A Microprocessor using basic block high speed buffer storage
07/11/2001CN1303043A Microprocessor possessing instruction for basic block high speed buffer storage of historical information
07/10/2001US6260172 Semiconductor device with logic rewriting and security protection function
07/10/2001US6260156 Method and system for managing bad areas in flash memory
07/10/2001US6260154 Apparatus for aligning clock and data signals received from a RAM
07/10/2001US6260151 Computer system capable of controlling the power supplied to specific modules
07/10/2001US6260143 Host-based caching method and system for copy protected content
07/10/2001US6260132 Method and apparatus for secure address re-mapping
07/10/2001US6260131 Method and apparatus for TLB memory ordering
07/10/2001US6260130 Cache or TLB using a working and auxiliary memory with valid/invalid data field, status field, settable restricted access and a data entry counter
07/10/2001US6260129 Management of fixed pages in memory for input/output operations
07/10/2001US6260123 Method and system for memory control and access in data processing systems
07/10/2001US6260122 Memory device
07/10/2001US6260121 Method for adaptive decoding of memory addresses