Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
12/2013
12/24/2013DE112004001781B4 Schaltung und Verfahren zum Codieren von in einem nichtflüchtigen Speicherarray zu speichernden Daten Circuit and method of encoding to be stored in a nonvolatile memory array data
12/24/2013DE102013210719A1 Verfahren und Systeme zum Verwalten von Cache-Speichern Methods and systems for managing caches
12/24/2013DE102006062383B4 Halbleiterspeicherelement und System für ein Halbleiterspeicherelement The semiconductor memory device and system for a semiconductor memory element
12/19/2013WO2013188754A1 A disambiguation-free out of order load store queue
12/19/2013WO2013188701A1 A method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization
12/19/2013WO2013188588A1 A lock-based and synch-based method for out of order loads in a memory consistency model using shared memory resources
12/19/2013WO2013188477A2 Storage control system with data management mechanism and method of operation thereof
12/19/2013WO2013188169A1 Erasure coding and replication in storage clusters
12/19/2013WO2013188168A1 Elimination of duplicate objects in storage clusters
12/19/2013WO2013188153A1 Two level addressing in storage clusters
12/19/2013WO2013188120A2 Zero cycle load
12/19/2013WO2013187862A1 A FAST MECHANISM FOR ACCESSING 2n±1 INTERLEAVED MEMORY SYSTEM
12/19/2013WO2013186888A1 Programmable controller and method for addressing electrical power disconnection
12/19/2013WO2013186831A1 Stream data processing method, stream data processing apparatus, and program
12/19/2013WO2013186828A1 Computer system and control method
12/19/2013WO2013186717A1 Managing accessing page table entries
12/19/2013WO2013186694A2 System and method for data classification and efficient virtual cache coherence without reverse translation
12/19/2013WO2013186647A1 Managing page table entries in a processing system
12/19/2013WO2013186646A1 Radix table translation of memory
12/19/2013WO2013186606A2 Compare and replace dat table entry
12/19/2013WO2013186605A1 Processor assist facility
12/19/2013WO2013186604A1 Constrained transaction execution
12/19/2013WO2013186015A1 Local clearing control
12/19/2013WO2013185638A1 Providing cache replacement notice using a cache miss request
12/19/2013WO2013185625A1 Information processing system, information processing method and memory system
12/19/2013WO2013090594A3 Infrastructure support for gpu memory paging without operating system integration
12/19/2013US20130339786 Smart active-active high availability das systems
12/19/2013US20130339756 Manufacturing method of a memory device to be authenticated
12/19/2013US20130339671 Zero cycle load
12/19/2013US20130339660 Method and apparatus for a partial-address select-signal generator with address shift
12/19/2013US20130339659 Managing accessing page table entries
12/19/2013US20130339658 Managing page table entries
12/19/2013US20130339657 Local clearing control
12/19/2013US20130339656 Compare and Replace DAT Table Entry
12/19/2013US20130339655 Translation look-aside table management
12/19/2013US20130339654 Radix Table Translation of Memory
12/19/2013US20130339653 Managing Accessing Page Table Entries
12/19/2013US20130339652 Radix Table Translation of Memory
12/19/2013US20130339651 Managing page table entries
12/19/2013US20130339650 Prefetch address translation using prefetch buffer
12/19/2013US20130339649 Single instruction multiple data (simd) reconfigurable vector register file and permutation unit
12/19/2013US20130339648 Method, apparatus, and computer program product for fast context switching of application specific processors
12/19/2013US20130339647 Computer system and data migration method
12/19/2013US20130339646 System, method and computer program product for utilizing code stored in a protected area of memory for securing an associated system
12/19/2013US20130339642 Saving/restoring selected registers in transactional processing
12/19/2013US20130339641 Integrated circuit chip and memory device
12/19/2013US20130339640 Memory system and soc including linear addresss remapping logic
12/19/2013US20130339638 Status polling of memory devices using an independent status bus
12/19/2013US20130339636 Storage-side storage request management
12/19/2013US20130339635 Reducing read latency using a pool of processing cores
12/19/2013US20130339634 Continuous page read for memory
12/19/2013US20130339633 Changing a system clock rate synchronously
12/19/2013US20130339632 Processor management method
12/19/2013US20130339631 Cross-threaded memory system
12/19/2013US20130339630 Monitoring a value in storage without repeated storage access
12/19/2013US20130339629 Tracking transactional execution footprint
12/19/2013US20130339628 Determining the logical address of a transaction abort
12/19/2013US20130339627 Monitoring a value in storage without repeated storage access
12/19/2013US20130339626 Prioritizing requests to memory
12/19/2013US20130339625 Cache memory prefetching
12/19/2013US20130339624 Processor, information processing device, and control method for processor
12/19/2013US20130339623 Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index
12/19/2013US20130339622 Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index
12/19/2013US20130339621 Address range priority mechanism
12/19/2013US20130339620 Providing Cache Replacement Notice Using a Cache Miss Request
12/19/2013US20130339619 System for reducing memory latency in processor
12/19/2013US20130339618 Avoiding aborts due to associativity conflicts in a transactional environment
12/19/2013US20130339617 Automatic pattern-based operand prefetching
12/19/2013US20130339616 Managing transactional and non-transactional store observability
12/19/2013US20130339615 Managing transactional and non-transactional store observability
12/19/2013US20130339614 Mitigating conflicts for shared cache lines
12/19/2013US20130339613 Storing data in a system memory for a subsequent cache flush
12/19/2013US20130339612 Apparatus and method for testing a cache memory
12/19/2013US20130339611 High-performance cache system and method
12/19/2013US20130339610 Cache line history tracking using an instruction address register file
12/19/2013US20130339609 Multilevel cache hierarchy for finding a cache line on a remote node
12/19/2013US20130339608 Multilevel cache hierarchy for finding a cache line on a remote node
12/19/2013US20130339607 Reducing store operation busy times
12/19/2013US20130339606 Reducing store operation busy times
12/19/2013US20130339605 Uniform storage collaboration and access
12/19/2013US20130339604 Highly Scalable Storage Array Management with Reduced Latency
12/19/2013US20130339601 System and method for dynamically resizing a parity declustered group
12/19/2013US20130339599 Methods and systems for adaptive queue depth management
12/19/2013US20130339598 Intelligent Active Vault Operation
12/19/2013US20130339597 Methods and apparatus providing high-speed content addressable memory (cam) search-invalidates
12/19/2013US20130339596 Cache set selective power up
12/19/2013US20130339595 Identifying and prioritizing critical instructions within processor circuitry
12/19/2013US20130339594 Host bus adapters with shared memory and battery backup
12/19/2013US20130339593 Reducing penalties for cache accessing operations
12/19/2013US20130339592 Approach to virtual bank management in dram controllers
12/19/2013US20130339591 Relaying apparatus, relay history recording method, and data processing apparatus
12/19/2013US20130339590 Semiconductor device with nonvolatile memory prevented from malfunctioning caused by momentary power interruption
12/19/2013US20130339589 Adaptive configuration of non-volatile memory
12/19/2013US20130339588 System on Chip with Reconfigurable SRAM
12/19/2013US20130339587 Storage system employing mram and array of solid state disks with integrated switch
12/19/2013US20130339586 Methods for adaptively programming flash memory devices and flash memory systems incorporating same
12/19/2013US20130339585 Management of Non-Volatile Memory Systems Having Large Erase Blocks
12/19/2013US20130339584 Method for accessing flash memory having pages used for data backup and associated memory device
12/19/2013US20130339583 Systems and methods for transferring data out of order in next generation solid state drive controllers
12/19/2013US20130339582 Flash Storage Controller Execute Loop
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