| Patents for G06F 11 - Error detection; Error correction; Monitoring (140,345) |
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| 05/18/1993 | US5212693 Small programmable array to the on-chip control store for microcode correction |
| 05/18/1993 | US5212692 Help function generation apparatus and method |
| 05/18/1993 | US5212587 Binary tree switching network |
| 05/18/1993 | CA1318030C Expert system for identifying failure points in a digital data processing system |
| 05/18/1993 | CA1318004C Single track orthogonal error correction system |
| 05/13/1993 | WO1993009494A1 Fault-tolerant computer processing using a shadow virtual processor |
| 05/13/1993 | WO1993009020A1 Process and device for dealing with errors in electronic control devices |
| 05/13/1993 | DE4136525A1 Electronic circuit testing for PCB mounted devices - reprogramming logic components for test function, stimulating circuit nodes for testing and reprogramming useful function |
| 05/13/1993 | DE4130704A1 Computer controlled system for obtaining and processing data in explosion hazardous environments - has several mains connection stages each with respective microswitch to isolate power rails during insertion or removal process |
| 05/12/1993 | EP0541508A2 Computer system |
| 05/12/1993 | EP0541381A2 Managing database recovery from failure |
| 05/12/1993 | EP0541345A1 Displaying dynamic control blocks |
| 05/12/1993 | EP0541288A2 Circuit module redundacy architecture |
| 05/12/1993 | EP0541281A2 Incremental-computer-file backup using signatures |
| 05/12/1993 | EP0540967A2 A method for generating test patterns for use with a scan circuit |
| 05/12/1993 | EP0509068A4 Dynamic association of rf radio data communication system in a pre-existing computer controlled network |
| 05/12/1993 | EP0393173B1 Data bus enable verification logic |
| 05/11/1993 | US5210871 Interprocessor communication for a fault-tolerant, mixed redundancy distributed information processing system |
| 05/11/1993 | US5210867 Method and apparatus for memory retry |
| 05/11/1993 | US5210866 Incremental disk backup system for a dynamically mapped data storage subsystem |
| 05/11/1993 | US5210865 Transferring data between storage media while maintaining host processor access for I/O operations |
| 05/11/1993 | US5210864 Pipelined microprocessor with instruction execution control unit which receives instructions from separate path in test mode for testing instruction execution pipeline |
| 05/11/1993 | US5210863 Multi-processor system for detecting a malfunction of a dual port memory |
| 05/11/1993 | US5210862 Bus monitor with selective capture of independently occuring events from multiple sources |
| 05/11/1993 | US5210861 Method for verifying a serializing function in a system including processors and a test system including processors for verifying the serializing function |
| 05/11/1993 | US5210860 Intelligent disk array controller |
| 05/11/1993 | US5210859 Program debugging support method and apparatus |
| 05/11/1993 | US5210854 System for updating program stored in eeprom by storing new version into new location and updating second transfer vector to contain starting address of new version |
| 05/11/1993 | US5210760 Optimized pointer control system |
| 05/11/1993 | US5210758 Means and method for detecting and correcting microinstruction errors |
| 05/11/1993 | US5210757 Method and apparatus for performing health tests of units of a data processing system |
| 05/11/1993 | US5210756 Fault detection in relay drive circuits |
| 05/11/1993 | US5210700 Automatic delay adjustment for static timing analysis |
| 05/11/1993 | US5210486 Circuit test method |
| 05/11/1993 | CA1317678C Dynamic progress marking icon |
| 05/06/1993 | DE4136338A1 Verfahren und vorrichtung zur fehlerbehandlung in elektronischen steuergeraeten Method and apparatus for error handling in electronic control units |
| 05/06/1993 | DE4135640A1 Triple redundancy computer system for data transfer - has three independently clocked computers linked to controller and common data bus, and logic circuit to compare block signals with threshold values to isolate faulty computer |
| 05/05/1993 | EP0540450A1 ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme |
| 05/05/1993 | EP0540152A1 Restriction checker generator |
| 05/05/1993 | EP0539827A2 A dynamic instruction modifying controller |
| 05/05/1993 | EP0539594A1 Control device for operating panel |
| 05/05/1993 | EP0539494A1 High-speed, high-capacity, fault-tolerant, error-correcting storage system for binary computers |
| 05/05/1993 | EP0539473A1 Error protection for vlc coded data |
| 05/05/1993 | CN1071772A Method for setting up system configuration in data processing system, data processing system, and expasion unit for data processing system |
| 05/05/1993 | CN1071770A Method and means for time zero backup copying of data |
| 05/04/1993 | US5208914 Method and apparatus for non-sequential resource access |
| 05/04/1993 | US5208814 Method and apparatus for operating an electronic reprographic printing system containing a job submit counter |
| 05/04/1993 | US5208813 On-line reconstruction of a failed redundant array system |
| 05/04/1993 | US5208782 Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement |
| 05/04/1993 | US5208776 Pulse generation circuit |
| 05/04/1993 | US5208742 Data line monitoring system |
| 05/04/1993 | US5208666 Error detection for digital television equipment |
| 04/29/1993 | WO1993008529A1 Method and means for time zero backup copying of data |
| 04/29/1993 | WO1993008528A1 System for backing-up data for rollback |
| 04/29/1993 | WO1993008524A1 System for dividing processing tasks into signal processor and decision-making microprocessor interfacing |
| 04/29/1993 | DE4234157A1 Semiconductor memory with ECC - has signal detectors connected so that they receive externally buffered signal |
| 04/29/1993 | DE4135000A1 Data back-up system for electronic computer networks - has server computer linked to workstations, two storage media accessible by server, and job controller to store back-up program |
| 04/28/1993 | EP0539313A2 Method and apparatus for simulating I/O devices |
| 04/28/1993 | EP0539200A2 Error detection for digital television equipment |
| 04/28/1993 | EP0539120A1 Source code analyzer |
| 04/27/1993 | US5206952 Fault tolerant networking architecture |
| 04/27/1993 | US5206948 Bus monitor with means for selectively capturing trigger conditions |
| 04/27/1993 | US5206943 Disk array controller with parity capabilities |
| 04/27/1993 | US5206938 Ic card with memory area protection based on address line restriction |
| 04/27/1993 | US5206866 Bit error correcting circuit for a nonvolatile memory |
| 04/27/1993 | US5206865 Error detection and correction memory system |
| 04/27/1993 | US5206861 System timing analysis by self-timing logic and clock paths |
| 04/27/1993 | US5206860 Recovery from a possible switching error in a computer i/o system |
| 04/27/1993 | US5206583 Latch assisted fuse testing for customized integrated circuits |
| 04/27/1993 | CA1317029C Method and apparatus for processing information data |
| 04/26/1993 | CA2079501A1 Error detection for digital television equipment |
| 04/25/1993 | CA2077772A1 Method for fault diagnosis by assessment of confidence measure |
| 04/21/1993 | EP0537903A2 Distributed control system |
| 04/21/1993 | EP0537899A1 Bus arbitration architecture incorporating deadlock detection and masking |
| 04/21/1993 | EP0537688A2 Power-up sequence system |
| 04/21/1993 | EP0537525A2 Computer system with reset function performing system reset after a power failure |
| 04/21/1993 | EP0537257A1 Integrated hierarchical representation of computer programs for a software development system |
| 04/21/1993 | EP0537204A1 Circuit arrangement for distributing on-chip generated test patterns with at least one scan path |
| 04/21/1993 | EP0182816B1 Fault tolerant, frame synchronization for multiple processor systems |
| 04/20/1993 | US5204964 Method and apparatus for resetting a memory upon power recovery |
| 04/20/1993 | US5204963 Method and apparatus for a backup power controller for volatile random access memory |
| 04/20/1993 | US5204956 Method and apparatus for monitoring the execution time of a computer program |
| 04/20/1993 | US5204864 Multiprocessor bus debugger |
| 04/20/1993 | US5204863 Device for monitoring the operation of a microprocessor system, or the like |
| 04/20/1993 | CA1316609C Method and apparatus for generating a start signal for parallel-synchronous operation of three substantially identical data processing units |
| 04/20/1993 | CA1316608C Arrangement for error recovery in a self-guarding data processing system |
| 04/19/1993 | CA2071346A1 Method and means for time zero backup copy of data |
| 04/16/1993 | CA2071301A1 Error detection and recovery in a dma controller |
| 04/15/1993 | WO1993007568A1 Setting up system configuration in a data processing system |
| 04/15/1993 | WO1993004432A3 High-performance dynamic memory system |
| 04/15/1993 | DE4233837A1 Dual lane computing system |
| 04/15/1993 | DE4233569A1 Error detection facility for multi processor system - has each processing module based upon two processors operating with delay and error determined by comparison of output |
| 04/14/1993 | EP0537098A2 Event handling mechanism having a filtering process and an action association process |
| 04/14/1993 | EP0536793A2 Personal computer using flash memory as BIOS-ROM |
| 04/14/1993 | EP0536375A1 Fault tolerant network file system |
| 04/13/1993 | US5203000 Power-up reset conditioned on direction of voltage change |
| 04/13/1993 | US5202988 System for communicating among processors having different speeds |
| 04/13/1993 | US5202980 Information processing system capable of readily taking over processing of a faulty processor |
| 04/13/1993 | US5202978 Self-test circuit of information processor |
| 04/13/1993 | US5202976 Method and apparatus for coordinating measurement activity upon a plurality of emulators |