CA1084126A - High-speed tone decoder utilizing a phase-locked loop - Google Patents

High-speed tone decoder utilizing a phase-locked loop

Info

Publication number
CA1084126A
CA1084126A CA270,572A CA270572A CA1084126A CA 1084126 A CA1084126 A CA 1084126A CA 270572 A CA270572 A CA 270572A CA 1084126 A CA1084126 A CA 1084126A
Authority
CA
Canada
Prior art keywords
signal
phase
controlled oscillator
tone decoder
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA270,572A
Other languages
French (fr)
Inventor
Robert R. Cordell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Application granted granted Critical
Publication of CA1084126A publication Critical patent/CA1084126A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/446Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using one signalling frequency

Abstract

HIGH-SPEED TONE DECODER UTILIZING
A PHASE LOCKED LOOP

Abstract of the Disclosure A narrow-band tone decoder has a controllable oscillator, connected in a fast-capture phase-locked loop, for generating a signal having a frequency determined by a control signal produced within the loop. A synchron-ous detector, which responds to an input signal of the tone decoder and to a signal from the controllable.
oscillator, produces a signal having a magnitude dependent upon the magnitudes of the input signal and of the signal from the controllable oscillator. A window comparator monitors the control signal within the loop for deciding when the generated signal is within a predetermined frequency range.

- i -

Description

-~ ~Q8~i26 , , Background of the Invention ~;
The invention is a narrow-band phase-locked loop tone decoder using a fast-capture phase-locked loop.
In the prior art, a phase-locked loop tone decoder, disclosed on pages 38-47 of a book, entitled Signetics Linear Phase Locked Loop Applications Book, 1972, uses a second order phase-locked loop. Such a loop includes a phase detector, a low-pass filter, and a controlled oscillator within the loop.
The low-pass filter determines both the capture range of the loop and the desired frequency detection range. The capture and detection ranges are coterminous. A synchronous detector -is arranged to respond to the input signal of the decoder and to the output of the oscillator for producing a strong output signal when the input signal tone and the oscillator output are in phase with one another.
For such tone decoders, the time required to capture an input signal varies inversely with the pass band of the filter in the second order phase-locked loop. Although the pass bandwidth can be made very narrow by selection of com-20 ponents of the low-pass filter, the speed of capture varies inversely with that bandwidth. Slow operation of the detector results from long time constants created by components required in the narrow-band low-pass filter.
If a signal is to be decoded in a brief period of time within a narrow detection band, such a second , ~
' -:

:, ~ .
q~ ~', ` 1~8~126 R. R~ Cordell 2 1 order phase-locked loop may not always capture th~ signal ~ 2 ~or decodin~ before the sign21 ~ 5 termlnated.
3 Thus, there 1~ a n~ed for a narrow-band tone 4 decoder arrangement which will determine wlthin a brief 5 period of tl~e whether or not an ap~lied 5~ gnal falls 6 within a predetermined narrow frequency ran~e.
7 Therefore it is an ob~ect to provide a fast- ;
8 operating narrow-band tone decoder.
g It is a further ob3ect to rapidly determlne 10 whether or not a received tone signal is within a narrow ~;

11 fr~uency band.
12 It is another ob~ect to provide an improved 13 phase-locked tone decoder.
14 Summary o~ the Tnventlon 1~ These and other ob~ects are realized by a tone 16 detector lncludin~ a controllable oscillator connected in 17 a phase-locked loop for generating a signzl ha~lng a 18 frequency determlned by a control slgnal produced within 19 th~ ~oop. A synchronous detector, responsive to an 20 input signal of the tone decoder and to a signal from 21 the controlled 03cillator, produces a signal having a 22 magnitude dependent upon the input signal and the signal 23 from the controllable oscillator. A circuit monitors 24 ~he control signal withln the loop for decld1ng when 25 the generated signal ls within a prede~ermined frequency 26 ran~e, 27 It ls a feature for a circuit monltorln~ the 28 control slgnal wlthln a phase-locked loop to decide wh~n 29 the frequency Or the signal eenerated by the controllable 3 oscillator ~f the loop is w~thin a predetermlned frequency 31 range~
- 2 -.

)84126 It is another feature to use a phase-locked loop -~
having a capture range substantially wider than the predetermined frequency range.
It is a further feature to use a first order phase-locked loop.
It is a still further feature to use a window comparator for monitoring the control signal within the phase-locked loop for deciding when the frequency of the signal generated by the controllable oscillator of the loop is within a predetermined frequency range.
In accordance with an aspect of the invention there is provided a tone decoder circuit comprising a controllable oscillator connected in a phase-locked loop for generating signals having a frequency determined by a control signal produced within the loop, the phase-locked loop having a capture range, a synchronous detector, responsive to an input signal of the tone decoder and to a first signal from the controlled oscillator, for producing a signal having a magnitude dependent upon the magnitudes of the ; 20 input signal and the first signal from the controllable oscillator, and means, connected to the loop and responsive to the control signal within the loop, for monitoring when the generated signal is within a predetermlned frequency range substantially narrower than ~ the capture range of the phase-locked loop, the monitoring means applying a signal to the synchronous detector for inhibiting the output of the synchronous detector when the first signal from the controlled oscillator is outside of . the predetermined frequency range.

-_ 3 _ 1~84~
Brief Description of the Drawings These and other objects and features of the invention may be more fully understood by reference to the following ~
detailed deseription when that description is read with ~,`
reference to the attached drawings wherein FIG. 1 is a block diagram of an illustrative embodiment of a tone deeoder arranged in aeeordance with the invention;
FIG. 2 is a block diagram of an alternative embodiment ~`
of a tone decoder arranged in aecordance with the invention;
FIG. 3 is a schematic diagram of an illustrative ~ :
window comparator;
FIGS. 4 and 5 are operating charaeteristies of the window eomparator;
FIG. 6 is an operating characteristie for the phase-loeked loops of the embodiments of FIGS. 1 and 2; and FIG. 7 is an operating characteristie for a prior art phase-locked loop.
.~
' :
~ ~

- 3a -10841Z~

Detailed Description ~
..
Referring now to FIG. 1, there is shown a fast operating narrow-band tone decoder circuit 10 for monitoring whether or not a signal received at terminal IN has a freq- ;~
uency within a predetermined range and has an amplitude exceeding a threshold for a specific period of time. An output signal is produced at a terminal OUT whenever the input signal has the appropriate combination of frequency, amplitude and duration. Otherwise no output signal is 10 produced. ~' The decoder circuit 10 includes a fast operating phase-locked loop 11 arranged in combination`with a window comparator 12 and a synchronous detector 13.
; The fast operating loop 11 is a simple first order phase-locked loop. It includes a phase detector 14 and a ' current controlled oscillator 16 interconnected in the loop by way of leads 18, 19, and 20 and a resistor 22.
... .
Phase detector 14 may be any selected one of a number of well known phase detectors which produce an output current signal. In a preferred embodiment of the invention, the selection is a double-balanced triangle comparator having a current-phase transfer characteristic with equal slopes of ;
opposite polarity recurring every cycle. Details of such a comparator, or phase detector, are described in an article entitled "A Precise Four-Quadrant Multiplier with Subnanosecond Response" by Barrie Gilbert, IEEE Journal of Solid-State Circuits, December 1968, pages 365-373, and are shown in :., .
schematic form in FIG. 8-34 of the aforementioned applications book~

- 1~8412:~ R. R. Cordell 2 1 The ph~se detector 14 recelves two input sl~nals.
2 One input Or such phase detector is a modiried input slgnal
3 that is applied double-rail by way of a pair of lead~ ~3 .. 4 to the tone decoder. .A dlfferentlal amplifier 26 is 5 interposed in the input circ~71try for modirying recei~Jed 6 ~np~t signals into low-level balanced square-wa~e 7 ~i~nal~ which are applied to the phase detector 14. ~he 8 dlfrerential ampllfier 26 provldeR voltage levél shifting 9 and preserves zero cross7ngs.of the input signal. A
lO second input to the phase detector 14 is applied from ll the 03cillator 16 by way of the palr o~ double-rail leads 12 20 to the phase detect~r 14. .0 13 The phase-locked loop ll locks on to any lnput ~-. 14 tone having, for a brlef interval, a reasonably hign ~ ;
15 amplitude and a frequency falling wlthin a wlde capture 16 range of the loop. The loop is able to rapidly capture ., .
17 lnput signals because lt is a first order loop. The 18 o~clllator 16 is the only first order network element l9 wlthin the loop. Leaa 18 conducts control current, 20 generated by the phase detector 14, through tne resistor 21 22 and the lead l9 to a control input of the current 22 controlled oscillator 16.

23 Because the tone detector is deslgned for tone 24 detecting applications, the oscillator should be a 25 stable one having a nominal operating frequency that 26 remalns close to the center of the deslred detection 27 range. A sultable oscillator ls de3cribed in detall in 28 U. S. patent 3,904,989, entitled HVoltage Controlled 29 Emitter-Coupled Multivibrator wlth Tem~erature 3 Compensatlon" and lssued in the name of R. R. Cordell.

.',. ...... '. ~.

--~` 1084126 ~., That patent describes a current-controlled oscillator arranged to operate at a frequency determined by a bias current which is an algebraic summation of the output current of a temperature dependent current source and a converter output signal current. The latter is supplied by a differential voltage-to-current converter.
In-the arrangement of FIG. 1 herein, the converter output signal current is replaced by the control current conducted through ~he resistor 22 and the lead 19 to the controlled ~; 10 oscillator 16.
Any change in the control current causes a corresponding change in the operating frequency of the oscillator. As a result, the frequency of oscillation locks on to the frequency of the modified input signal which is applied by way of the pair of leads 23. ;~
In the phase-locked loop 11, capture of the input signal frequency occurs verX rapidly because only the voltage dropping resistor 22 and a parallel capacitor 24 are connected directly in the path between the phase detector 14 and the oscillator 16. There are no capac-itive nor resistive paths to shunt control current away ; from the oscillator.
There are two outputs resulting from the - controlled oscillator 16. It and a phase shifter 25, ~; which is responsive to the output of the oscillator 16, produce output signals having the same frequency but different phases, respectively, on the pairs of leads 20 and 28. In an actual embodiment of the invention, the phase shift operation was accomplished within the associated 30 oscillator circuit. ~

~, . . .
The first output occurs on the pair of leads 28.
During phase lock the signals on the leads 28 are substan-tially in phase with the modified input signals on the leads 23.
The second output of the oscillator 16 occurs on the leads 20. During phase lock the signals on leads 20 are substantially 90 degrees out of phase with the signals on leads 28. The phase difference between the signals on leads 20 and 28 may be any of a wide range of differences; how- r ever, a phase difference of approximately 90 degrees can be achieved readily in practice.
The oscillator output signal on the pair of leads -~
20 together with the modified input signal on the pair of leads 23 are applied as inputs to the phase detector 14. Any difference between the frequency or phase of the modified input signal and the frequency or phase of the oscillator output signal generates the control signal current in lead 18. Polarity of the control current depends upon the relative frequencies and phases of the input and oscillator signals.
The window comparator 12 is inserted in the decoder circuit for monitoring the control signal current produced by the phase detector 14 to decide when the signal generated by the controllable oscillator 16 is within a predetermined frequency range. The comparator 12 decides -about the frequency of signals from oscillator 16 by moni-toring voltage drop across resistor 22, which is caused by the control signal current in the leads 18 and 19. In the prior art, on the other hand, the detection range was determined by what frequencies passed through a low-pass filter included within the loop. The tone detector circuit arrangement 10 of FIG. 1, being a faster responding first : . , ' . .,' -:' . ' ' 108412~; ~

- order network, has a distinct advantage over the slower responding second order network of the prior art.
Referring now to FIG. 3, there is shown an exemplary schematic diagram for the window comparator 12.
Input to the window comparator is through a differential voltage comparator including transistors 30 and 31. Another transistor 32 is a constant current source for the differ-ential voltage comparator. Constant current sources 34 and 35 are connected in the collector circuits of the transistors 30 and 31, respectively. Each of the current sources 34 and 35 is arranged to supply more current than the current conducted through its associated transistor 30 or 31 when the differential amplifier is balanced. At such a time, the current sources 34 and 35 are saturated, and output switching transistors 37 and 38 are disabled. These output switching transistors are disabled at balance because of lack of base drive current.
Resistor 22 of FIG. 1, which is in series circuit -between lead 18 at the output of the phase detector 14 and lead 19 at the input of the controllable oscillator 16, is shown in FIG. 3 connected directly to the base electrodes , of the transistors 30 and 31 of the window comparator 12.
Voltage drop created by the control current signal conducted - from the phase detector 14 of FIG. 1 through the resistor 22 to the current controlled oscillator 16 controls the operation of the window comparator 12.
As shown in FIGS. 4 and 5, the window comparator operates in three different states in response to varying voltage drop across the resistor 22. An enabling signal, i.e., no output current, is produced by the window com-parator on a lead 40 when the controlled oscillator signal is within the predetermined frequency range, as indicated 108412!6 by the magnitude of the voltage drop across the resistor 22. A muting signal, i.e., a high level current I40, is -produced on the lead 40 when the oscillator signal is out- ;.
side of the predetermined frequency range, also indicated by the magnitude of voltage drop across the resistor 22.
Referring now to FIG. 6, there is shown a diagram of the control current characteristic as a function of the oscillator frequency. In FIG. 6 it is noted that ,, , ~ the detection range is substantially narrower than the .:, .. .
~ 10 capture range. The limits of the range for detection are - indicated on the horizontal frequency axis. Those limits determine the magnitude of control current of both polarities and define the window. The limits of the window are conver-ted to difference voltages in FIGS. 4 and 5.
~ hen the input signal frequency equals the center frequency fO of the oscillator, the control current is nil and the voltage drop across resistor 22 is zero. The differential pair is balanced and comparator currents I1 and I2 are equal. Since the differential amplifier is balanced in this state, the current sources 34 and 35 are saturated, and the transistors 37 and 38 are disabled. No ; output current is conducted through either of the transistors 37 and 38, or on lead 40 to a control terminal of the synchronous detector 13. This lack of current in the lead 40 indicates that the output frequency of the current controlled oscillator 16 is within the predetermined frequency range.
When the input signal frequency deviates from the center frequency of the controlled oscillator 16, some control current from the phase detector 14 of FIG. 1 is conducted through the resistor 22 to the controlled _ g _ - . .. , ,. : :: , -1~841Z6 oscillator. The resulting voltage drop of either polarity across the resistor 22 unbalances the differential amplifier, including transistors 30 and 31 of FIG. 3, causing unequal currents in their collector circuits. For example, if the ;
unbalance is small enough so that the transistor 30, having ~ r a higher input voltage, fails to conduct as much current as supplied by its collector current source 34, both of the transistors 37 and 38 remain disabled. This is also true if transistor 31 has a higher input voltage but fails to conduct as much current as its current source 35. No :
; current is conducted from the transistors 37 and 38 through the lead 40 to the control terminal of the synchronous detector 13 of FIG. 1. This condition like the previously described balanced condition indicates that the frequency of the output signal from the controlled oscillator is within the predetermined frequency detection range.
When the input signal frequency differs substan-tially from the center frequency of the oscillator, more control current is conducted from the phase detector 14 through the resistor 22 to the oscillator 16. The voltage drop across the resistor 22 sufficiently unbalances the differential amplifier, including transistors 30 and 31, so that one of those transistors conducts more current than is supplied by the current source in its collector circuit. Assuming that the transistor 31 is conducting more current than that supplied by source 35 at such a time, base-emitter current is conducted through the transistor 38 enabling it to conduct. Transistor 38 then supplies output current I40 through the muting lead 40 to the synchronous detector 13 of FIG. 1. That current inhibits any output signal from the synchronous detector indicating 10841~6 that the oscillator signal is outside of the predetermined frequency detection range.
As previously mentioned, the control current -~
through the resistor 22 of FIG. 1 is one component of the bias current that controls the frequency of oscillation of the current controlled oscillator 16. ;
Bandwidth of the predetermined frequency detection range can be varied by the selection of the magnitude of the resistor 22.
The capacitor 24 is bridged across resistor 22 in FIGS. 1 and 3 for providing a high frequency short across the resistor 22 so that the window comparator responds only to the average value of the control current.
Synchronous detector 13 may be any selected one of a number of conventional detectors similar to the one selected as phase detector 14. The synchronous detector is responsive to the modified input signal on leads 23 and to the first output of the controlled oscillator 16. The first output of the oscillator 16, occurring on the leads 28, drives one input of the synchronous detector 13. The second output of the oscillator 16 on leads 20 drives one input of the phase detector. A second input of the phase detector 14 and a second input of the synchronous detector 13 are driven by the modified input signal on leads 23.
When the input signal on leads 23 has an amplitude exceeding a predetermined threshold for a predetermined duration, the synchronous detector 13 produces an output signal if the input signal is within the predetermined frequency range. Enabling and muting signals produced by the window comparator 12 are coupled through the lead 40 to the synchronous detector 13 for enabling output of that detector when the oscillator output frequency is within the desired range and for muting output of that detector when the oscillator frequency is out of that range.
Output signals from the synchronous detector 13 are coupled by way of a lead 42 to a filter capacitor 45 '~
and to a threshold comparator 50. The capacitor 45 is connected between the lead 42 and ground for shunting high frequency signals to ground while passing low frequency -10 signals to the threshold comparator 50. A reference voltage ~ -VR is applied to the other input of the threshold comparator 50 for determining the ratio of "turn on" ~-delay relative to "turn off" delay.
Signals from the synchronous detector, which ` have sufficient amplitude for the selected interval of time, exceed the threshold voltage VR and switch the output of the threshold comparator 50 indicating that the oscillator is in lock with the input signal and that the oscillator and input signals are within the predetermined frequency range.
In FIG. 1, an input terminal 4Oa of the threshold comparator is shown to indicate that muting and enabling signals from the window comparator 12 can be applied to the threshold comparator rather than to the synchronous detector 13. At the choice of the designer, the lead 40 from the window comparator can be connected by way of terminal 4Oa to the threshold comparator for muting output signals. ~' Whether one chooses to apply muting and enabling signals to the synchronous detector or to the threshold comparator, the muting and enabling signals can be .

:` ` 1~84126 ~ :

utilized in an opposite sense than the sense described inthe foregoing description. In the opposite sense, the synchronous detector 13 or the threshold comparator 50 would be disabled when the oscillator frequency is within the desired range and enabled when the oscillator frequency is out of the range.
Referring now to FIG. 2, there is shown an illustrative arrangement of a fast operating phase-locked tone decoder 54 in which the phase-locked loop includes a voltage controlled oscillator 56 in place of the current controlled oscillator 16, shown in FIG. 1. Except for voltage controlled oscillator 56 and some filtering circuitry coupling the feedback loop to the window .
comparator 12, the rest of the arrangement is identical with the circuit of FIG. 1. The designators of FIG. 1 ~ `
are used in FIG. 2 for designating like components.
A resistor 62 is connected between the lead 18 in series with one input of the window comparator 12. A
capacitor 63 develops a voltage drop for operating the window comparator 12 similarly to *he way it operates in the arrangement of FIG. 1. The resistor 62 and the capacitor 63, however, form a low-pass filter which advantageously has a much wider bandwidth than filters used in the narrow-band phase-locked loop tone decoders .

~ 1084126 R. R. Cord~ll 2 L od~ ~he p~ior ~rt.. The presence, of this filter does no~ j ec~ the.operatlon Or the phase-loc}ced loop because the e~ ls n~t-in the loop~
4 The frequencY range is measured by the wlndow C9mpa~a~D~ 1~. rather than being established by the low-pass er.. The- w~der bandwldth of the filter, lncluding re~t~ 6æ and capacitor 63 ln FIG. 2, enable~ faster & d~t~t~ ,o~: ~he. input si~nals~ This fast operatlon 9- ena~-les ~he~de~oder to rapidly detect short duration tones 19: hE~ing æ fr,e~uency within the predetermlned bandw~dth. ,~
1~ ~e~r~ing now to FIG. 7, there i8 sho~m a 1~ c~a~c~r~stic curve o~ a prior art phase lock circu~t.
13 ~I~ . r sho~s- csntrol current versus ~requency of the '' L4- os-c~ *or.-a~-i~ FIG. 6. It is noted, however~ that the ca~ture- ~ang~.and.the detection range are equal for the ' ;-l~ p~iDr~ ar~:whereas the detection range is much narrower U~ tha~-the ca~,tur.e.range for the illustrative embod~ments of 1~' the:sub~,ect-invention.
1~ The above-detailed description is lllustrat-v~
2~: of~s~me.-embodiments of the invention, and lt is to be -21: unders.t~od that-additional embodiments thereof wlll be 22 0~19us t~.those.s~illed in the art. The ~mbod~ments 2~ described.herein, together with those additional 2~- embodiments,.a~P considered to be withln the scope of the 25,- inv~ti~n..
2~-2~
2~.
2~
3~- .
3~

.

.
, ' -- -

Claims (13)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A tone decoder circuit comprising a controllable oscillator connected in a phase-locked loop for generating signals having a frequency determined by a control signal produced within the loop, the phase-locked loop having a capture range, a synchronous detector, responsive to an input signal of the tone decoder and to a first signal from the controlled oscillator, for producing a signal having a magnitude dependent upon the magnitudes of the input signal and the first signal from the controllable oscillator, and means, connected to the loop and responsive to the control signal within the loop, for monitoring when the generated signal is within a predetermined frequency range substantially narrower than the capture range of the phase-locked loop, the monitoring means applying a signal to the synchronous detector for inhibiting the output of the synchronous detector when the first signal from the controlled oscillator is outside of the predetermined frequency range.
2. A tone decoder circuit in accordance with claim 1 further comprising means for comparing the magnitude of the signal produced by the synchronous detector with a reference value and for showing when the first signal generated by the controlled oscillator is within the predetermined frequency range and that the input signal of the tone decoder has an amplitude exceeding a predetermined threshold.
3. A tone decoder circuit in accordance with claim 2 wherein the phase-locked loop comprises a current controlled oscillator, a phase detector responsive to the input signal of the tone decoder and to a second signal from the controlled oscillator for producing the control signal as a current within the loop, the second signal being of different phase than the first signal from the controlled oscillator, and means for coupling the control signal current to the current controlled oscillator, and, the monitoring means comprise a window comparator responsive to the control signal current for applying the indicating signal to the synchronous detector.
4. A tone decoder circuit in accordance with claim 3 wherein the window comparator produces the indicating signal as a uniform signal in response to the control signal current when the input signal frequency is outside of the predetermined frequency range.
5. A tone decoder circuit in accordance with claim 2 wherein the phase-locked loop comprises a voltage controlled oscillator, a phase detector responsive to the input signal of the tone decoder and to a second signal from the controlled oscillator for producing the control signal as a voltage, the second signal being of a different phase than the first signal from the controlled oscillator, and means for coupling the control signal voltage to the voltage controlled oscillator, and the monitoring means comprise a window comparator responsive to the control signal voltage for applying the indicating signal to the synchronous detector.
6. A tone decoder in accordance with claim 1 wherein the phase-locked loop is a first order loop.
7. A tone decoder circuit comprising a controllable oscillator connected in a phase-locked loop for generating signals having a frequency determined by a control signal produced within the loop, the phase-locked loop having a capture range, a synchronous detector, responsive to an input signal of the tone decoder and to a first signal from the controlled oscillator, for producing a signal having a magnitude dependent upon the magnitudes of the input signal and the first signal from the controllable oscillator, and means, connected to the loop and responsive to the control signal within the loop, for monitoring when the generated signal is within a predetermined frequency range substantially narrower than the capture range of the phase-locked loop, the monitoring means applying a signal to the synchronous detector for inhibiting the output of the synchronous detector when the first signal from the controlled oscillator is within the predetermined frequency range.
8. A tone decoder circuit in accordance with claim 7 further comprising means for comparing the magnitude of the signal produced by the synchronous detector with a reference value and for showing when the first signal from the controlled oscillator is within the predetermined frequency range and that the input signal of the tone decoder has an amplitude exceeding a predetermined threshold.
9. A tone decoder circuit comprising a controllable oscillator connected in a phase-locked loop for generating signals having a frequency determined by a control signal produced within the loop, the phase-locked loop having a capture range, a synchronous detector, responsive to an input signal of the tone decoder and to a first signal from the controlled oscillator, for producing a signal having a magnitude dependent upon the magnitudes of the input signal and the first signal from the controllable oscillator, means, connected to the loop and responsive to the control signal within the loop, for monitoring when the generated signal is within a predetermined frequency range substantially narrower than the capture range of the phase-locked loop, and means for comparing the magnitude of the signal produced by the synchronous detector with a reference value and for showing when an input signal of the tone decoder has an amplitude exceeding a predetermined threshold, the monitoring means applying an indicating signal to the comparing means for inhibiting the output of the comparing means when the first signal from the controlled oscillator is outside of the predetermined frequency range.
10. A tone decoder circuit in accordance with claim 9 wherein the phase-locked loop comprises a current controlled oscillator, a phase detector responsive to the input signal of the tone decoder and to a second signal from the controlled oscillator for producing the control signal as a current within the loop, the second output signal being out of phase with the first signal from the controlled oscillator, means for coupling the control signal current to the current controlled oscillator, and the monitoring means comprise a window comparator responsive to the control signal current for applying the indicating signal to the comparing means.
11. A tone decoder circuit in accordance with claim 10 wherein the window comparator produces the indicating signal as a uniform signal in response to the control signal current when the input signal frequency is outside of the predetermined frequency range.
12. A tone decoder circuit in accordance with claim 8 wherein the phase-locked loop comprises a voltage controlled oscillator, a phase detector responsive to the input signal of the tone decoder and to a second signal from the controlled oscillator for producing the control signal as a voltage, the second signal being out of phase with the first signal from the controlled oscillator, and means for coupling the control signal voltage to the voltage controlled oscillator, and the monitoring means comprise a window-comparator responsive to the control signal voltage for applying the indicating signal to the comparing means.
13. A tone decoder circuit comprising a controllable oscillator connected in a phase-locked loop for generating signals having a frequency determined by a control signal produced within the loop, the phase-locked loop having a capture range, a synchronous detector, responsive to an input signal of the tone decoder and to a first signal from the controlled oscillator, for producing a signal having a magnitude dependent upon the magnitudes of the input signal and the first signal from the controllable oscillator, means, connected to the loop and responsive to the control signal within the loop, for monitoring when the generated signal is within a predetermined frequency range substantially narrower than the capture range of the phase-locked loop, and means for comparing the magnitude of the signal produced by the synchronous detector with a reference value and for showing when an input signal of the tone decoder has an amplitude exceeding a predetermined threshold, the monitoring means applying an indicating signal to the comparing means for inhibiting the output of the comparing means when the first signal from the controlled oscillator is within the predetermined frequency range.
CA270,572A 1976-02-17 1977-01-27 High-speed tone decoder utilizing a phase-locked loop Expired CA1084126A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US658,728 1976-02-17
US05/658,728 US4037171A (en) 1976-02-17 1976-02-17 High speed tone decoder utilizing a phase-locked loop

Publications (1)

Publication Number Publication Date
CA1084126A true CA1084126A (en) 1980-08-19

Family

ID=24642435

Family Applications (1)

Application Number Title Priority Date Filing Date
CA270,572A Expired CA1084126A (en) 1976-02-17 1977-01-27 High-speed tone decoder utilizing a phase-locked loop

Country Status (9)

Country Link
US (1) US4037171A (en)
JP (1) JPS5845868B2 (en)
BE (1) BE851437A (en)
CA (1) CA1084126A (en)
DE (1) DE2706429A1 (en)
FR (1) FR2341989A1 (en)
GB (1) GB1574961A (en)
IT (1) IT1072732B (en)
NL (1) NL7701635A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4159527A (en) * 1978-01-19 1979-06-26 Tokyo Shibaura Electric Co., Ltd. Wave generator
US4215427A (en) * 1978-02-27 1980-07-29 Sangamo Weston, Inc. Carrier tracking apparatus and method for a logging-while-drilling system
US4230910A (en) * 1978-08-11 1980-10-28 Tii Corporation Signalling and channel loop test circuits for station carrier telephone system
JPS594332A (en) * 1982-06-30 1984-01-11 Nec Home Electronics Ltd Bit clock generating circuit
JPS6348019A (en) * 1986-08-15 1988-02-29 Nec Corp Fm signal discriminating circuit
US4855683A (en) * 1987-11-18 1989-08-08 Bell Communications Research, Inc. Digital phase locked loop with bounded jitter
US5422911A (en) * 1993-09-17 1995-06-06 Motorola, Inc. Frequency walled phase lock loop
DE59900216D1 (en) * 1998-10-22 2001-10-04 Contraves Space Ag Zuerich Device for the homodyne reception of optical phase-shifted signals
US7209532B2 (en) * 2002-03-28 2007-04-24 Harris Corporation Phase lock loop and method for coded waveforms

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2930892A (en) * 1954-03-26 1960-03-29 Sperry Rand Corp Demodulator for a phase or frequency modulated signal
US3080533A (en) * 1959-01-29 1963-03-05 Gen Electric Phase-lock oscillator
US3199037A (en) * 1962-09-25 1965-08-03 Thompson Ramo Wooldridge Inc Phase-locked loops
US3336534A (en) * 1965-02-08 1967-08-15 Hughes Aircraft Co Multi-phase detector and keyed-error detector phase-locked-loop
US3456196A (en) * 1966-12-30 1969-07-15 Bell Telephone Labor Inc Digital automatic frequency control system
GB1361783A (en) * 1971-09-10 1974-07-30 Marconi Instruments Ltd Frequency synchronisers
US3952261A (en) * 1972-11-06 1976-04-20 Fujitsu Ltd. Signal detection circuit
US3922602A (en) * 1974-10-11 1975-11-25 Motorola Inc Lock detector for a phase locked loop

Also Published As

Publication number Publication date
FR2341989A1 (en) 1977-09-16
JPS5845868B2 (en) 1983-10-13
US4037171A (en) 1977-07-19
GB1574961A (en) 1980-09-17
IT1072732B (en) 1985-04-10
NL7701635A (en) 1977-08-19
JPS52100808A (en) 1977-08-24
DE2706429A1 (en) 1977-08-18
BE851437A (en) 1977-05-31
FR2341989B1 (en) 1982-10-29

Similar Documents

Publication Publication Date Title
US5091921A (en) Direct conversion receiver with dithering local carrier frequency for detecting transmitted carrier frequency
US4205272A (en) Phase-locked loop circuit for use in synthesizer tuner and synthesizer tuner incorporating same
US6160444A (en) Demodulation of FM audio carrier
CA1084126A (en) High-speed tone decoder utilizing a phase-locked loop
CA2073347C (en) Apparatus and method for generating quadrature signals
US4316154A (en) Automatic sweep and acquisition circuit for a phase locked loop
EP0645891B1 (en) Frequency tuning for a phase locked loop
US3993958A (en) Fast acquisition circuit for a phase locked loop
US4525686A (en) Phase-locked loop circuit with variable bandwidth filter
Thomason et al. An inexpensive method to stabilize the frequency of a CO2 laser
US5774555A (en) Switched capacitor bandpass filter for detecting pilot signal
US4488120A (en) Frequency shift keying demodulator using a phase locked loop and voltage comparator
US4318055A (en) Digitally controlled phase lock distillator system
US3775695A (en) Phase lock loop for a voltage controlled oscillator
US4482869A (en) PLL Detection circuit having dual bandwidth loop filter
EP0302290B1 (en) Automatic frequency control system
Biswas et al. Heterodyne phase locked loops-revisited
JPH0249060B2 (en)
JPH0879013A (en) Switched capacitor band-pass filter for pilotsignal detection
US4796102A (en) Automatic frequency control system
JP2693775B2 (en) Video receiving circuit
JP3254009B2 (en) Circuit including phase locked loop
JP2513329B2 (en) Frequency modulated wave receiver
US3501705A (en) Phase-lock loop fm detector circuit employing a phase comparator and keyed oscillator
KR0138363B1 (en) Voltage controlling oscillator

Legal Events

Date Code Title Description
MKEX Expiry